SASIMI 2018: THE 21ST WORKSHOP ON SYNTHESIS AND SYSTEM INTEGRATION OF MIXED INFORMATION TECHNOLOGIES
PROGRAM

Days: Monday, March 26th Tuesday, March 27th

Monday, March 26th

View this program: with abstractssession overview

09:20-10:20 Session K: Keynote Speech
Chair:
Mineo Kaneko (Japan Advanced Institute of Science and Technology, Japan)
09:20
Peter Marwedel (TU Dortmund, Germany)
Cyber-Physical Systems: Opportunities, Challenges, and (Some) Solutions ( abstract ) ( pdf )
10:20-12:00 Session R1: Regular Poster Session I
Chairs:
Masashi Imai (Hirosaki University, Japan)
Koyo Nitta (NTT, Japan)
10:20
Hsin-I Wu (National Tsing Hua University, Taiwan)
Chi-Kang Chen (Industrial Technology Research Institute, Taiwan)
Da-Yi Guo (National Tsing Hua University, Taiwan)
Ren-Song Tsay (National Tsing Hua University, Taiwan)
[R1-1]
A Highly Efficient Virtualization-Assisted Approach for Full-System Virtual Prototypes ( abstract ) ( pdf )
10:22
Saki Hatta (NTT, Japan)
Nobuyuki Tanaka (NTT, Japan)
Takeshi Sakamoto (NTT, Japan)
[R1-2]
Area-efficient Programmable Finite-state Machine Toward Next Generation Access Network SoC ( abstract ) ( pdf )
10:24
Kenshi Ito (Osaka University, Japan)
Yoshinori Takeuchi (Osaka University, Japan)
[R1-3]
Performance Analysis of Temporal Codings for Spiking Neural Network ( abstract ) ( pdf )
10:26
Pin-Xin Liao (National Tsing Hua University, Taiwan)
Ting-Chi Wang (National Tsing Hua University, Taiwan)
[R1-4]
A Bus-Aware Global Router ( abstract ) ( pdf )
10:28
Chih-Ko Yang (National Chiao Tung University, Taiwan)
Hao-Chiao Hong (National Chiao Tung University, Taiwan)
[R1-5]
A Firmware for Improving the Writing Performance of Multi-Chip MLC NAND Flash Memory Systems ( abstract )
10:30
Yuki Tanaka (Kyoto University, Japan)
Song Bian (Kyoto University, Japan)
Masayuki Hiromoto (Kyoto University, Japan)
Takashi Sato (Kyoto University, Japan)
[R1-6]
A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring ( abstract )
10:32
Wakako Nakano (Kwansei Gakuin University, Japan)
Nagisa Ishiura (Kwansei Gakuin University, Japan)
[R1-7]
Extended Distributed Control for Dynamic Scheduling across Dataflow Graphs ( abstract ) ( pdf )
10:34
Shinya Kuwamura (FUJITSU LABORATORIES LTD., Japan)
Satoshi Kazama (FUJITSU LABORATORIES LTD., Japan)
Eiji Yoshida (FUJITSU LABORATORIES LTD., Japan)
Junji Ogawa (FUJITSU LABORATORIES LTD., Japan)
Takashi Miyoshi (FUJITSU LABORATORIES LTD., Japan)
Yasuo Noguchi (FUJITSU LABORATORIES LTD., Japan)
[R1-8]
Near-Data Processing for Genome Analysis Using Software-Controlled SSD ( abstract )
10:36
Nobutaka Kito (Chukyo University, Japan)
Yurie Koketsu (Chukyo University, Japan)
Kazuyoshi Takagi (Kyoto University, Japan)
[R1-9]
Designs of Component Circuits for Stochastic Computing Using Rapid Single Flux Quantum Circuits ( abstract ) ( pdf )
10:38
Shogo Matsumoto (Kyoto University, Japan)
Hidenori Gyoten (Kyoto University, Japan)
Masayuki Hiromoto (Kyoto University, Japan)
Takashi Sato (Kyoto University, Japan)
[R1-10]
A Feasibility Study of Annealing Processor for Fully-Connected Ising Model Based on Memristor/CMOS Hybrid Architecture ( abstract )
10:40
Hiroyuki Baba (Fukuoka University, Japan)
Tongxin Yang (Fukuoka University, Japan)
Masahiro Inoue (Fukuoka University, Japan)
Kaori Tajima (Fukuoka University, Japan)
Tomoaki Ukezono (Fukuoka University, Japan)
Toshinori Sato (Fukuoka University, Japan)
[R1-11]
A Carry-Predicting Full Adder for Accuracy-Scalable Computing ( abstract ) ( pdf )
10:42
Hongjie Xu (Kyoto University, Japan)
Jun Shiomi (Kyoto University, Japan)
Tohru Ishihara (Kyoto University, Japan)
Hidetoshi Onodera (Kyoto University, Japan)
[R1-12]
A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits ( abstract )
10:44
Kazuyuki Sakata (Renesas Electronics Corporation, Japan)
Takashi Hasegawa (Sony LSI Design, Japan)
Kouji Ichikawa (DENSO CORPORATION, Japan)
Toshiki Kanamoto (Hirosaki University, Japan)
[R1-13]
Prediction of the Impact of Mutual Inductance on Timing Towards Nano-scale SoC ( abstract ) ( pdf )
10:46
Jon T. Butler (Naval Postgraduate School, United States)
Tsutomu Sasao (Meiji University, Japan)
[R1-14]
Analysis of Cyclic Row-Shift Decompositions for Index Generation Functions ( abstract )
10:48
Takumi Okamoto (Hiroshima University, Japan)
Tetsushi Koide (Hiroshima University, Japan)
Toru Tamaki (Hiroshima University, Japan)
Bisser Raytchev (Hiroshima University, Japan)
Kazufumi Kaneda (Hiroshima University, Japan)
Shigeto Yoshida (Medical Corporation JR Hiroshima Hospital, Japan)
Hiroshi Mieno (Medical Corporation JR Hiroshima Hospital, Japan)
Shinji Tanaka (Hiroshima University Hospital, Japan)
[R1-15]
Investigation of Real-Time Computer-Aided Diagnosis system using CNN feature and SVM identifier with Colorectal Endoscopic Images ( abstract ) ( pdf )
10:50
Akito Hoshide (The University of Kitakyushu, Japan)
Bo Liu (The University of Kitakyushu, Japan)
Shigetoshi Nakatake (The University of Kitakyushu, Japan)
[R1-16]
An Implementation of Low-cost Wireless Sensor Network for Wide-area Disaster ( abstract )
10:52
Ayano Takezaki (Kobe University, Japan)
Shogo Ohmura (Kobe University, Japan)
Naoki Katayama (Kobe University, Japan)
Tetsuya Hirose (Kobe University, Japan)
Nobutaka Kuroki (Kobe University, Japan)
Masahiro Numa (Kobe University, Japan)
[R1-17]
An Error Diagnosis Technique Based on Unsatisfiable Cores to Extract Error Locations Sets ( abstract )
10:54
Chi-Kang Chen (Industrial Technology Research Institute, Taiwan)
Hsin-I Wu (National Tsing Hua University, Taiwan)
Cheng-Lin Tsai (National Tsing Hua University, Taiwan)
Ren-Song Tsay (National Tsing Hua University, Taiwan)
[R1-18]
A Reuse-Distance Based Approach for Early-Stage Multi-level Cache Design Optimization ( abstract ) ( pdf )
12:00-13:30Lunch Break
13:30-14:20 Session I1: Invited Talk I
Chair:
Akihiko Miyazaki (NTT, Japan)
13:30
Sri Parameswaran (The University of New South Wales, Australia)
Heterogeneous Multi-Processor Pipelines: a Real-Time MPSoC Story ( abstract ) ( pdf )
14:20-16:00 Session R2: Regular Poster Session II
Chairs:
Masato Inagi (Hiroshima City university, Japan)
Tomoaki Ukezono (Fukuoka University, Japan)
14:20
Satoru Maruyama (Ritsumeikan University, Japan)
Ankur Gupta (IIT Roorkee, India)
Sudip Roy (IIT Roorkee, India)
Shigeru Yamashita (Ritsumeikan University, Japan)
[R2-1]
Placement of Reagents on Programmable Microfluidic Devices ( abstract )
14:22
Yuuki Imai (Kyoto University, Japan)
Tohru Ishihara (Kyoto University, Japan)
Hidetoshi Onodera (Kyoto University, Japan)
Akihiko Shinya (NTT, Japan)
Shota Kita (NTT, Japan)
Kengo Nozaki (NTT, Japan)
Kenta Takata (NTT, Japan)
Masaya Notomi (NTT, Japan)
[R2-2]
An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters ( abstract )
14:24
Kodai Abe (Ritsumeikan University, Japan)
Kentaro Haneda (Ritsumeikan University, Japan)
Shigeru Yamashita (Ritsumeikan University, Japan)
[R2-3]
On Optimization Methods for Decision Diagrams to Represent Probabilities ( abstract )
14:26
Yuto Ishihara (Saitama University, Japan)
Shinichi Nishizawa (Saitama University, Japan)
Kazuhito Ito (Saitama University, Japan)
[R2-4]
Minimization of Equality Check for Soft Error Detection in DMR Design Implemented with Error Correction by Operation Re-execution ( abstract ) ( pdf )
14:28
Qiaochu Zhao (Osaka University, Japan)
Ittetsu Taniguchi (Osaka University, Japan)
Makoto Nakamura (Laboratory of Hi-Think Corporation, Japan)
Takao Onoye (Osaka University, Japan)
[R2-5]
An Efficient Parts Counting Method based on Intensity Distribution Analysis for Industrial Vision Systems ( abstract ) ( pdf )
14:30
Juinn-Dar Huang (National Chiao Tung University, Taiwan)
Chia-Hung Liu (National Chiao Tung University, Taiwan)
Wei-Hao Yang (National Chiao Tung University, Taiwan)
[R2-6]
Versatile Ring-Based Architecture for General-Purpose Digital Microfluidic Biochips ( abstract )
14:32
Takuya Yamauchi (ams Japan Co., Ltd., Japan)
Tetsuro Okura (ams Japan Co., Ltd., Japan)
[R2-7]
A Deep Neural Network Based Approach to Achieve Aesthetic Schematics ( abstract ) ( pdf )
14:34
Daiki Hara (National Institute of Technology Nagano College, Japan)
Takefumi Yoshikawa (National Institute of Technology Nagano College, Japan)
[R2-8]
A Low Power Data Bus Architecture by Charge Recycling Utilization on Single-Ended Transmission Line ( abstract )
14:36
Takashi Imagawa (Ritsumeikan University, Japan)
Takahiro Ikeshita (Hokkaido University, Japan)
Hiroshi Tsutsui (Hokkaido University, Japan)
Yoshikazu Miyanaga (Hokkaido University, Japan)
[R2-9]
Hardware Design Exploration of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication ( abstract )
14:38
Yuuta Satomi (Hirosaki University, Japan)
Koutaro Hachiya (Teikyo Heisei University, Japan)
Masashi Imai (Hirosaki University, Japan)
Toshiki Kanamoto (Hirosaki University, Japan)
Kaoru Furumi (Hirosaki University, Japan)
Atsushi Kurokawa (Hirosaki University, Japan)
[R2-10]
Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm ( abstract )
14:40
Fu-Lian Wong (Yuan Ze University, Taiwan)
Li-Cheng Zheng (Yuan Ze University, Taiwan)
Yung-Chih Chen (Yuan Ze University, Taiwan)
[R2-11]
Node Merging for Threshold Logic Network Optimization ( abstract )
14:42
Yuki Arai (Chuo University, Japan)
Shuji Tsukiyama (Chuo University, Japan)
[R2-12]
A Heuristic Method for Delay Insertion to Improve Clock Period of General-Synchronous Circuit and Its Evaluation ( abstract ) ( pdf )
14:44
Naoki Osako (Kwansei Gakuin University, Japan)
Sayuri Ota (Kwansei Gakuin University, Japan)
Suguru Yura (Kwansei Gakuin University, Japan)
Nagisa Ishiura (Kwansei Gakuin University, Japan)
[R2-13]
High-Level Synthesis of Side Channel Attack Resistant RSA Decryption Circuit ( abstract ) ( pdf )
14:46
Hong-Yan Su (National Chiao Tung University, Taiwan)
Yan-Shiun Wu (National Chiao Tung University, Taiwan)
Yi-Hsiang Chang (National Tsing Hua University, Taiwan)
Rasit Onur Topaloglu (IBM, United States)
Yih-Lang Li (National Chiao Tung University, Taiwan)
[R2-14]
MapReduce-Based Pattern Classification for Design Space Analysis ( abstract )
14:48
Dave Y.-W. Lin (National Chiao Tung University, Taiwan)
Charles H.-P. Wen (National Chiao Tung University, Taiwan)
[R2-15]
Radiation-Hardened Design by Delay-Controllable Flip-Flops for Soft-Error-Rate Mitigation ( abstract )
14:50
Shunsuke Negoro (Ritsumeikan University, Japan)
Daichi Sukezane (Ritsumeikan University, Japan)
Atsuya Shibata (Ritsumeikan University, Japan)
Kotaro Maekawa (Ritsumeikan University, Japan)
Ittetsu Taniguchi (Osaka University, Japan)
Hiroyuki Tomiyama (Ritsumeikan University, Japan)
[R2-16]
Measurement and Modeling of Quadcopter Energy with ROS ( abstract )
14:52
Infall Syafalni (Logic Research Co., Ltd., Japan)
Katsuhiko Wakasugi (Logic Research Co., Ltd., Japan)
Tongxin Yang (Logic Research Co., Ltd., Japan)
Tsutomu Sasao (Meiji University, Japan)
Xiaoqing Wen (Kyushu Institute of Technology, Japan)
[R2-17]
Netlist Conversion from Customer Logic Interface Format (CLIF) to Verilog for Legacy Circuits ( abstract )
14:54
Masaki Fujikawa (Kogakuin University, Japan)
Kouki Takayama (Kogakuin University, Japan)
Shingo Fuchi (Aoyama Gakuin University, Japan)
[R2-18]
Anti-counterfeiting and Authenticity Verification Technique for Molded Synthetic Resin Products ( abstract ) ( pdf )
16:00-17:30 Session D: Panel Discussion

“What is the next place to go, in the era of IoT and AI?”

Moderator:
Prof. Robert Dutton (Stanford University)

Panelist:
Prof. Peter Marwedel (Technische Universitat Dortmund)
Prof. Sri Parameswaran (University of New South Wales)
Prof. Elena Dubrova (Royal Institute of Technology)
Prof. Iris Hui-Ru Jiang (National Taiwan University)

Synopsis:
Wherever we go, we cannot avoid seeing these two terms: IoT and AI. Starting with short talks by experts in the domains related to synthesis and system  integration, we will discuss, in the era of IoT and AI, what are challenges and pitfalls in those domains, and also directions we should go in the long run.

Organizer:
Prof. Kiyoharu Hamaguchi (Shimane University)

( pdf )

Tuesday, March 27th

View this program: with abstractssession overview

09:10-10:00 Session I2: Invited Talk II
Chair:
Hiroshi Saito (University of Aizu, Japan)
09:10
Elena Dubrova (Royal Institute of Technology, Sweden)
Lightweight Cryptographic Primitives for Resource-Constrained Devices ( abstract ) ( pdf )
10:00-11:50 Session R3: Regular Poster Session III
Chairs:
Hiromitsu Awano (The University of Tokyo, Japan)
Masanori Muroyama (Tohoku University, Japan)
10:00
Salita Sombatsiri (NEC Corporation, Japan)
Seiya Shibata (NEC Corporation, Japan)
Yuki Kobayashi (NEC Corporation, Japan)
Hiroaki Inoue (NEC Corporation, Japan)
Takashi Takenaka (NEC Corporation, Japan)
Takeo Hosomi (NEC Corporation, Japan)
[R3-1]
Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks ( abstract ) ( pdf )
10:02
Zuitoku Shin (Kyoto University, Japan)
Shumpei Morita (Kyoto University, Japan)
Song Bian (Kyoto University, Japan)
Michihiro Shintani (Nara Institute of Science and Technology, Japan)
Masayuki Hiromoto (Kyoto University, Japan)
Takashi Sato (Kyoto University, Japan)
[R3-2]
Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence ( abstract )
10:04
Shuhei Ishino (Tokyo University of Agriculture and Technology, Japan)
Mitsuru Hasegawa (Tokyo University of Agriculture and Technology, Japan)
Kunihiro Fujiyoshi (Tokyo University of Agriculture and Technology, Japan)
[R3-3]
A Method of Layout Pattern Classification Using Clustering ( abstract ) ( pdf )
10:06
Yu-Guang Chen (Yuan Ze University, Taiwan)
Kun-Wei Chiu (National Cheng Kung University, Taiwan)
Ing-Chao Lin (National Cheng Kung University, Taiwan)
[R3-4]
A Novel NBTI-Aware Wake-up Strategy for Power-Gated Designs ( abstract )
10:08
Chunfeng Liu (Technical University of Munich, Germany)
Tsung-Yi Ho (National Tsing Hua University, Taiwan)
[R3-5]
Test Vector Generation for Microfluidic Fully Programmable Valve Arrays (FPVAs) ( abstract )
10:10
Yi-Jung Chen (National Chi Nan University, Taiwan)
Wen-Wei Chang (National Chi Nan University, Taiwan)
Chia-Yin Liu (National Chi Nan University, Taiwan)
Bo-Yuan Chen (National Chi Nan University, Taiwan)
Ming-Ying Tsai (National Chi Nan University, Taiwan)
[R3-6]
Processor and Memory Co-Allocation for MPSoCs with Single-ISA Heterogeneous Multi-Core Architecture ( abstract )
10:12
Louis Y.-Z. Lin (National Chiao Tung University, Taiwan)
Charles H.-P. Wen (National Chiao Tung University, Taiwan)
[R3-7]
Accelerating Deterministic Parallel Test Pattern Generation by Hiding Latency Among Multi-threads ( abstract )
10:14
Li-Chin Chen (NCTU Taiwan, Taiwan)
Hung-Ming Chen (NCTU Taiwan, Taiwan)
[R3-8]
Learning to Predict DRC Violations During Placement ( abstract )
10:16
Kazuho Katsumata (Japan Advanced Institute of Science and Technology, Japan)
Junghoon Oh (Japan Advanced Institute of Science and Technology, Japan)
Mineo Kaneko (Japan Advanced Institute of Science and Technology, Japan)
[R3-9]
Register Binding in Datapath Synthesis Considering Post-Silicon Skew Tunability ( abstract )
10:18
Tadaaki Tanimoto (Renesas Electronics Corporation, Japan)
[R3-10]
Differential Update of Automotive Control Device Firmware ( abstract )
10:20
Ying-Chi Wei (National Chiao Tung University, Taiwan)
Hong-Yan Su (National Chiao Tung University, Taiwan)
Radhamanjari Samanta (National Chiao Tung University, Taiwan)
Yih-Lang Li (National Chiao Tung University, Taiwan)
[R3-11]
LESAR: A Dynamic Line-End Spacing Aware Detailed Router ( abstract )
10:22
Chung-Cheng Su (National Chiao Tung University, Taiwan)
Yi-Cheng Hsieh (National Chiao Tung University, Taiwan)
Jia-Heng Chang (National Chiao Tung University, Taiwan)
Chung-Chih Hung (National Chiao Tung University, Taiwan)
[R3-12]
A 12-bit 10MS/s SAR ADC with Mixed Switching and Background Offset Calibration ( abstract )
10:24
Yu-Yi Wu (Chung Yuan Christian University, Taiwan)
Shih-Hsu Huang (Chung Yuan Christian University, Taiwan)
[R3-13]
Test Wrapper Chain Design for Three-Dimensional SoCs under TSV Count Constraint ( abstract )
10:26
Tetsuaki Fujimoto (Ritsumeikan University, Japan)
Wataru Takahashi (NEC Corporation, Japan)
Kazutoshi Wakabayashi (NEC Corporation, Japan)
Takashi Imagawa (Ritsumeikan University, Japan)
Hiroyuki Ochi (Ritsumeikan University, Japan)
[R3-14]
Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch ( abstract )
10:28
Chun-Chia Kuo (CMSC, Inc., Taiwan)
Yi-Yu Liu (National Taiwan University of Science and Technology, Taiwan)
[R3-15]
Voltage-drop Aware Timing Analysis for Pessimism Design Constraint Prevention ( abstract ) ( pdf )
10:30
Tsutomu Sasao (Meiji University, Japan)
Kyu Matsuura (Meiji University, Japan)
Yukihiro Iguchi (Meiji University, Japan)
[R3-16]
A Method to Identify Affine Equivalence Classes of Logic Functions ( abstract )
10:32
Soichiro Ito (Ritsumeikan University, Japan)
Yoshiki Tsuchida (Ritsumeikan University, Japan)
Masahiro Fukui (Ritsumeikan University, Japan)
[R3-17]
Development and Evaluation of a Magnetic Resonant Coupling Wireless Power Transfer System for Multiple Receivers ( abstract ) ( pdf )
10:34
Saki Yamaguchi (University of Kitakyushu, Japan)
Yasuhiro Takashima (University of Kitakyushu, Japan)
[R3-18]
Relaxed Routing Problem with Constraint Satisfaction Problem ( abstract ) ( pdf )
10:36
Masashi Imai (Hirosaki University, Japan)
Naoya Onizawa (Tohoku University, Japan)
Takahiro Hanyu (Tohoku University, Japan)
Tomohiro Yoneda (National Institute of Informatics, Japan)
[R3-19]
Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing ( abstract )
11:50-13:20Lunch Break
13:20-14:10 Session I3: Invited Talk III
Chair:
Yukihide Kohira (The University of Aizu, Japan)
13:20
Iris Hui-Ru Jiang (National Taiwan University, Taiwan)
Timing is Everything! ( abstract ) ( pdf )
14:10-16:00 Session R4: Regular Poster Session IV
Chairs:
Nobutaka Kito (Chukyo University, Japan)
Kenshu Seto (Tokyo City University, Japan)
14:10
Yuta Nagaoka (Kyoto University, Japan)
Tohru Ishihara (Kyoto University, Japan)
Hidetoshi Onodera (Kyoto University, Japan)
[R4-1]
Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation ( abstract )
14:12
Ryota Uematsu (Hokkaido University, Japan)
Kota Ando (Hokkaido University, Japan)
Kodai Ueyoshi (Hokkaido University, Japan)
Kazutoshi Hirose (Hokkaido University, Japan)
Masayuki Ikebe (Hokkaido University, Japan)
Tetsuya Asai (Hokkaido University, Japan)
Shinya Takamaeda-Yamazaki (Hokkaido University, Japan)
Masato Motomura (Hokkaido University, Japan)
[R4-2]
Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform ( abstract )
14:14
Jin Liu (Osaka University, Japan)
Masahide Hatanaka (Osaka University, Japan)
Takao Onoye (Osaka University, Japan)
[R4-3]
A Collision Mitigation Method on Spatial Reuse for WLAN in a Dense Residential Environment ( abstract ) ( pdf )
14:16
Tomoya Fujii (Tokyo Institute of Technology, Japan)
Shimpei Sato (Tokyo Institute of Technology, Japan)
Hiroki Nakahara (Tokyo Institute of Technology, Japan)
[R4-4]
A Design Algorithm for a Neuron Pruning Toward a Compact Binarized Deep Convolution Neural Network on an FPGA ( abstract )
14:18
Daijiro Murooka (The University of Kitakyushu, Japan)
Xuechen Zang (The University of Kitakyushu, Japan)
Taisei Kubo (The University of Kitakyushu, Japan)
Yasuhiro Takashima (The University of Kitakyushu, Japan)
Shigetoshi Nakatake (The University of Kitakyushu, Japan)
[R4-5]
Post-silicon Skew Tuning by Programmable Delay Element with Variability Analysis ( abstract )
14:20
Takumi Egawa (Kyoto University, Japan)
Tohru Ishihara (Kyoto University, Japan)
Hidetoshi Onodera (Kyoto University, Japan)
Akihiko Shinya (NTT, Japan)
Shota Kita (NTT, Japan)
Kengo Nozaki (NTT, Japan)
Kenta Takata (NTT, Japan)
Masaya Notomi (NTT, Japan)
[R4-6]
A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies ( abstract )
14:22
Ping Lei (Waseda University, Japan)
Shinji Kimura (Waseda University, Japan)
[R4-7]
RF-SM: Random Forest Training Process Acceleration with Subsampling Method on FPGA ( abstract ) ( pdf )
14:24
Yusuke Nozaki (Meijo University, Japan)
Masaya Yoshikawa (Meijo University, Japan)
[R4-8]
Power Analysis Method for a Lightweight Cipher Midori ( abstract )
14:26
Kano Akagi (Tokyo Institute of Technology, Japan)
Shimpei Sato (Tokyo Institute of Technology, Japan)
Atsushi Takahashi (Tokyo Institute of Technology, Japan)
[R4-9]
Target Pin-Pair Selection Algorithm Using Minimum Maximum-Edge-Weight Matching for Set-Pair Routing ( abstract ) ( pdf )
14:28
Loo Shean Liu (National Central University, Taiwan)
Hsin-Ju Hsu (National Central University, Taiwan)
Hao-Yu Chang (National Central University, Taiwan)
Chien-Nan Jimmy Liu (National Central University, Taiwan)
Jing-Yang Jou (National Central University, Taiwan)
[R4-10]
Hardware Implementation of WDF-Based Analog Circuit Emulation ( abstract )
14:30
Toshitaka Ito (Hiroshima City University, Japan)
Yuri Itotani (Hiroshima City University, Japan)
Shin'Ichi Wakabayashi (Hiroshima City University, Japan)
Shinobu Nagayama (Hiroshima City University, Japan)
Masato Inagi (Hiroshima City University, Japan)
[R4-11]
An FPGA-based Nearest Neighbor Search Engine Using Distance-based Hashing for High-Dimensional Data ( abstract )
14:32
Sayaka Terashima (Keio University, Japan)
Takuya Kojima (Keio University, Japan)
Hayate Okuhara (Keio University, Japan)
Yusuke Matsushita (Keio University, Japan)
Naoki Ando (Keio University, Japan)
Mitaro Namiki (Graduate School of Technology, Tokyo University of Agriculture and Technology, Japan)
Hideharu Amano (Keio University, Japan)
[R4-12]
A Shared Memory Chip for Twin-Tower of Chips ( abstract )
14:34
Tetsuo Miyauchi (Japan Advanced Institute of Science and Technology, Japan)
Kiyofumi Tanaka (Japan Advanced Institute of Science and Technology, Japan)
[R4-13]
Building a Framework for an Application-Adaptive Processor System on FPGA-based SoC ( abstract ) ( pdf )
14:36
Zih-Ming Yeh (Chung Yuan Christian University, Taiwan)
Wei-Kai Cheng (Chung Yuan Christian University, Taiwan)
[R4-14]
Hybrid Cross Mesh Synthesis with Register Clustering ( abstract )
14:38
Kiyoharu Hamaguchi (Shimane University, Japan)
Yosuke Kakiuchi (HIroshima Institute of Technology, Japan)
Ryosuke Takakura (Shimane University, Japan)
[R4-15]
Applying Bayesian Network-Based Machine Learning to Regression Design Verification ( abstract )
14:40
Yoshiki Tsuchida (Ritsumeikan University, Japan)
Haruya Fujii (Ritsumeikan University, Japan)
Tomoki Abe (Ritsumeikan University, Japan)
Lei Lin (Ritsumeikan University, Japan)
Masahiro Fukui (Ritsumeikan University, Japan)
[R4-16]
Motor Modeling, and Simulation of the Driving Performance of an EV-cart with the Motor ( abstract )
14:42
Kosei Yamaguchi (Ritsumeikan University, Japan)
Takashi Imagawa (Ritsumeikan University, Japan)
Hiroyuki Ochi (Ritsumeikan University, Japan)
[R4-17]
Routing Method Considering Programming Constraint of Reconfigurable Device Using Via-switch Crossbars ( abstract )
14:44
Jukiya Furushima (The University of Aizu, Japan)
Tatsuki Otake (The University of Aizu, Japan)
Hiroshi Saito (The University of Aizu, Japan)
[R4-18]
Performance Optimization by Placement Constraints for FPGA-based Asynchronous Processors ( abstract ) ( pdf )
14:46
Kaoru Furumi (Hirosaki University, Japan)
Shintaro Okamoto (Hirosaki University, Japan)
Toshiki Kanamoto (Hirosaki University, Japan)
Masashi Imai (Hirosaki University, Japan)
Atsushi Kurokawa (Hirosaki University, Japan)
[R4-19]
Impact of Distributing 3D Stacked ICs on Maximum Temperature Reduction ( abstract )
16:00-16:50 Session I4: Invited Talk IV
Chair:
Kiyoharu Hamaguchi (Shimane University, Japan)
16:00
Jun Deguchi (Toshiba Memory Corp., Japan)
Time-Domain Neural Network for Deep Learning Inference ( abstract ) ( pdf )