| Abstract | A modern chip often contains large numbers of pre-designed macros
(e.g., embedded memories, IP blocks) and standard cells, with very different sizes. The fast-growing design complexity with large-scale mixed-size macros and standard cells has caused significant challenges to modern circuit placement. In this paper, we first discuss the strengths and weaknesses of existing techniques for mixed-size placement. We then present a unified analytical algorithm to place large macros and standard cells simultaneously, with the first attempt in the literature to resolve the two intrinsic problems in analytical macro placement: rotation and legalization of large macros. Comparative studies are provided to show the superiority of our unified analytical algorithm. Finally, we provide some future research directions for modern mixed-size placement. |