| Title | Placing Static and Stack Data into a Scratch-Pad Memory for Reducing the Energy Consumption of Multi-task Applications |
| Author | *Lovic Gauthier, Tohru Ishihara (Kyushu Univ., Japan), Hideki Takase (Nagoya Univ., Japan), Hiroyuki Tomiyama (Ritsumeikan Univ., Japan), Hiroaki Takada (Nagoya Univ., Japan) |
| Page | pp. 7 - 12 |
| Detailed information (abstract, keywords, etc) | |
| Title | Aggressive Register Unsharing with Selective FU Sharing in High-Level Synthesis |
| Author | *Yuko Hara-Azumi, Toshinobu Matsuba (Nagoya Univ., Japan), Hiroyuki Tomiyama (Ritsumeikan Univ., Japan), Shinya Honda, Hiroaki Takada (Nagoya Univ., Japan) |
| Page | pp. 13 - 18 |
| Detailed information (abstract, keywords, etc) | |
| Title | Automatic Generation for Efficient Software TLM at Multiple Abstraction Layers |
| Author | Meng-Huan Wu, *Yi-Shan Lu, Wen-Chuan Lee, Chen-Yu Chuang, Ren-Song Tsay (National Tsing Hua Univ., Taiwan) |
| Page | pp. 19 - 24 |
| Detailed information (abstract, keywords, etc) | |
| Title | Evaluation of Two Operating Systems for Lego Mindstorms NXT |
| Author | *Wing-Kwong Wong, Fu-Hsien Lin (National Yunlin Univ. of Science and Tech., Taiwan) |
| Page | pp. 25 - 30 |
| Detailed information (abstract, keywords, etc) | |
| Title | Concord: A Configurable SoC Prototyping Platform |
| Author | Chih-Chyau Yang, *Chen-Yen Lin, Hui-Ming Lin, Yui-Chih Shih, Hsi-Tse Wu, Shi-Lun Chen, Tien-Ching Wang, Chien-Ming Wu, Chun-Ming Huang, Chin-Long Wey (National Chip Implementation Center, Taiwan) |
| Page | pp. 31 - 36 |
| Detailed information (abstract, keywords, etc) | |
| Title | Generation Method of Decomposed Small Area Instruction Decoder for Configurable Processor |
| Author | *Hiroki Ohsawa, Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan) |
| Page | pp. 37 - 41 |
| Detailed information (abstract, keywords, etc) | |
| Title | A High-speed VLSI Architecture of Output Probability and Likelihood Score Computations for HMM-based Recognition Systems |
| Author | *Ryo Shimazaki, Kazuhiro Nakamura, Mashatoshi Yamamoto, Kazuyoshi Takagi (Nagoya Univ., Japan), Naofumi Takagi (Kyoto Univ., Japan) |
| Page | pp. 42 - 47 |
| Detailed information (abstract, keywords, etc) | |
| Title | Improved Local Horizontal and Vertical Common Subexpression Elimination Method for Constant Multiple Multiplication |
| Author | *Yasuhiro Takahashi, Toshikazu Sekine (Gifu Univ., Japan), Michio Yokoyama (Yamagata Univ., Japan) |
| Page | pp. 48 - 53 |
| Detailed information (abstract, keywords, etc) | |
| Title | Improved Normalized Image Reconstruction for Iris Recognition |
| Author | *Hyo Jin Nam, Harsh Durga Tiwari, Yong Beom Cho (Konkuk Univ., Republic of Korea) |
| Page | pp. 54 - 57 |
| Detailed information (abstract, keywords, etc) | |
| Title | Inter-Island Delay Aware Communication Synthesis for Island-Based Distributed Register Architecture |
| Author | Juinn-Dar Huang, *Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou (National Chiao Tung Univ., Taiwan) |
| Page | pp. 58 - 63 |
| Detailed information (abstract, keywords, etc) | |
| Title | MorFPGA: A Modularized FPGA-Based Embedded System Development Platform |
| Author | Yu-Tsang Chang, Chun-Ming Huang, Chien-Ming Wu, Chun-Yu Chen, *Yu-Sheng Lin, Chih-Ting Kuo, Ting-Chun Liu, Chin-Long Wey (National Chip Implementation Center, Taiwan) |
| Page | pp. 64 - 69 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Novel Design-Methodology for PCB Traces Ensuring High Signal-Integrity on Random Signals |
| Author | *Masami Ishiguro, Shohei Akita, Hiroki Shimada, Noriyuki Aibe (Univ. of Tsukuba, Japan), Ikuo Yoshihara (Univ. of Miyazaki, Japan), Moritoshi Yasunaga (Univ. of Tsukuba, Japan) |
| Page | pp. 70 - 75 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Novel IR-Drop Tolerant Scheduling for Reliability-Aware Datapaths |
| Author | *Keisuke Inoue, Mineo Kaneko (JAIST, Japan) |
| Page | pp. 76 - 81 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Physics-Based Compact Model for the 1/f Noise in p-type Si/SiGe/Si Heterostructure MOSFETs |
| Author | *Chia-Yu Chen (Stanford Univ., U.S.A.), Chi-Chao Wang, Yun Ye (Arizona State Univ., U.S.A.), Yang Liu (Stanford Univ., U.S.A.), Junko Sato-Iwanaga, Akira Inoue, Haruyuki Sorada (Panasonic Electronics, Japan), Yu Cao (Arizona State Univ., U.S.A.), Robert Dutton (Stanford Univ., U.S.A.) |
| Page | pp. 82 - 83 |
| Detailed information (abstract, keywords, etc) | |
| Title | On Behavioral Modeling for Sigma-Delta Digital-to-Analog Converters with Accurate Timing Response |
| Author | *Hsin-Yu Luo, Hsiu-Wen Li, Xiao-Qian Chang, Chien-Nan Jimmy Liu (National Central Univ., Taiwan) |
| Page | pp. 84 - 89 |
| Detailed information (abstract, keywords, etc) | |
| Title | Self-Tuning Metric and Control Policy to Optimally Trade-off Lifetime Performance-Power-Reliability |
| Author | *Evelyn Mintarno, Joelle Skaf (Stanford Univ., U.S.A.), Rui Zheng, Jyothi Velamala, Yu Cao (Arizona State Univ., U.S.A.), Stephen Boyd, Robert W. Dutton, Subhasish Mitra (Stanford Univ., U.S.A.) |
| Page | pp. 90 - 95 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Throughput-aware BusMesh NoC Configuration Algorithm Utilizing the Communication Rate between IP Cores |
| Author | *SeungJu Lee, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ., Japan) |
| Page | pp. 96 - 101 |
| Detailed information (abstract, keywords, etc) | |
| Title | TSV-constrained Scan Chain Reordering for 3D ICs |
| Author | Wei-Ting Chen, Chia-Ching Chang, *Charles H.-P. Wen (National Chiao Tung Univ., Taiwan) |
| Page | pp. 102 - 107 |
| Detailed information (abstract, keywords, etc) | |