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The 16th Workshop on Synthesis And System Integration of Mixed Information Technologies

Paper Session IV: System Level Design and Design Experience (II)
Time: 15:15 - 16:50 Tuesday, October 19, 2010
Location: Ballroom
Chairs: Masanori Muroyama (Tohoku Univ., Japan), Lih-Yih Chiou (National Cheng Kung Univ., Taiwan)

R4-1 (Time: 15:15 - 15:17)
TitleA Regular Expression Matching Circuit Based on a Modular Non-Deterministic Finite Automaton with Multi-Character Transition
Author*Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech., Japan)
Pagepp. 359 - 364
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R4-2 (Time: 15:17 - 15:19)
TitleAcceleration of a SAT Based Solver for Minimum Cost Satisfiability Problems Using Optimized Boolean Constraint Propagation
Author*Xin Zhang (Waseda Univ., Japan), Peilin Liu (Shanghai Jiao Tong Univ., China), Shinji Kimura (Waseda Univ., Japan)
Pagepp. 365 - 370
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R4-3 (Time: 15:19 - 15:21)
TitleCircuit Synthesis for Fast Memory Access in System LSI
Author*Kazuya Kishida, Takashi Kambe (Kinki Univ., Japan)
Pagepp. 371 - 376
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R4-4 (Time: 15:21 - 15:23)
TitleClock Gating Optimization with Delay-Matching Cells
Author*Shih-Jung Hsu, Rung-Bin Lin (Yuan Ze Univ., Taiwan)
Pagepp. 377 - 382
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R4-5 (Time: 15:23 - 15:25)
TitleDesign and Evaluation of Digital Receiver for Low Power Wireless Communication
Author*Kazuki Ohya, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Pagepp. 383 - 388
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R4-6 (Time: 15:25 - 15:27)
TitleDesign and Verification of an Ultra-Low-Power Active RFID Tag with Multiple Power Domains
Author*Kenichi Agawa, Massimo Alioto, Wenting Zhou, Tsung-Te Liu, Louis Alarcon, Kimiya Hajkazemshirazi, Mervin John, Jesse Richmond, Wen Li, Jan Rabaey (Univ. of California, Berkeley, U.S.A.)
Pagepp. 389 - 394
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R4-7 (Time: 15:27 - 15:29)
TitleDevice Simulation and Experimental Measurement of High-Voltage Unified-CBiCMOS Buffer Driver for Ultra-High-Speed CCD Image Sensors
AuthorToshiaki Koike-Akino (Harvard Univ., U.S.A.), Takashi Hamahata, *Toshiro Akino, Takeharu Goji Etoh (Kinki Univ., Japan)
Pagepp. 395 - 400
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R4-8 (Time: 15:29 - 15:31)
TitleEfficient Multiple Regular Expression Matching on FPGAs based on Extended SHIFT-AND Method
Author*Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, Yoshikazu Miyanaga (Hokkaido Univ., Japan)
Pagepp. 401 - 406
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R4-9 (Time: 15:31 - 15:33)
TitleEnergy-Aware Partitioning Using a Multi-Objective Genetic Algorithm
AuthorLih-Yih Chiou, Yi-Siou Chen, *Ya-Lun Jian (National Cheng Kung Univ., Taiwan)
Pagepp. 407 - 411
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R4-10 (Time: 15:33 - 15:35)
TitleAn Extension of Systolic Regular Expression Matching Hardware for Handling Iteration of Strings Using Quantifiers
Author*Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ., Japan)
Pagepp. 412 - 417
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R4-11 (Time: 15:35 - 15:37)
TitleA Novel Timing Synchronization Method for Fast and Accurate Multi-Core Instruction-Set Simulators
AuthorMeng-Huan Wu, *Fan-Wei Yu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Pagepp. 418 - 423
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R4-12 (Time: 15:37 - 15:39)
TitleA Power Efficient Unified Gated Flip-Flop
Author*Takumi Okuhira, Tohru Ishihara (Kyushu Univ., Japan)
Pagepp. 424 - 429
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R4-13 (Time: 15:39 - 15:41)
TitleQuantitative Graph-Based Minimal Queue Sizing for Throughput Optimization in Latency-Insensitive Designs
AuthorJuinn-Dar Huang, *Yi-Hang Chen, Ya-Chien Ho (National Chiao Tung Univ., Taiwan)
Pagepp. 430 - 435
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R4-14 (Time: 15:41 - 15:43)
TitleA Reconfigurable Layout Method and Evaluation for Network On Chip
Author*Yuichi Nakamura (NEC Corp., Japan), Marcello Lajolo (NEC, U.S.A.)
Pagepp. 436 - 441
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R4-15 (Time: 15:43 - 15:45)
TitleRER: a Tuning Tool for Implementing a Computational Pipeline Across Multiple FPGAs
AuthorHirokazu Morishita, *Kenta Inakagata (Keio Univ., Japan), Yasunori Osana (Seikei Univ., Japan), Naoyuki Fujita (JAXA, Japan), Hideharu Amano (Keio Univ., Japan)
Pagepp. 442 - 447
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R4-16 (Time: 15:45 - 15:47)
TitleSoft-error Tolerability Analysis for Triplicated Circuit on an FPGA
Author*Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ., Japan)
Pagepp. 448 - 453
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R4-17 (Time: 15:47 - 15:49)
TitleA Tile Based Reconfigurable Architecture with Dual ALU-array/Processor Operating Mode Capability
AuthorShin'ichi Kouyama, Masayuki Hiromoto (Kyoto Univ., Japan), Yukihiro Nakamura (Ritsumeikan Univ., Japan), *Hiroyuki Ochi (Kyoto Univ., Japan)
Pagepp. 454 - 459
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R4-18 (Time: 15:49 - 15:51)
TitleVLSI Architecture of V-AMDF based Pitch Detection for Tonal Speech Recognizer
Author*Jirabhorn Chaiwongsai, Werapon Chiracharit, Kosin Chamnongthai (King Mongkut’s Univ. of Tech. Thonburi, Thailand), Yoshikazu Miyanaga (Hokkaido Univ., Japan), Kohji Higuchi (Univ. of Electro-Communications, Japan)
Pagepp. 460 - 465
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