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SASIMI 2012
The 17th Workshop on Synthesis And System Integration of Mixed Information Technologies

Poster III
Time: 10:00 - 11:45 Friday, March 9, 2012
Location: Int'l Conf. Room & Mtg. Room 31
Chairs: Qiang Zhu (Cadence Design Systems, Japan), Kyungsoo Lee (Kyoto Univ., Japan)

R3-1
TitleReplacement of Flip-Flops by Latches and Pulsed Latches for Power and Timing Optimization
AuthorYao-Ting Wu, *Rung-Bin Lin (Yuan Ze Univ., Taiwan)
Pagepp. 300 - 304
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R3-2
TitleA Routability-oriented Packing Method for FPGA with Fracturable Logic Elements
AuthorWei Chen (Waseda Univ., Japan), Yuichi Nakamura (NEC Corp., Japan), *Nan Liu, Takeshi Yoshimura (Waseda Univ., Japan)
Pagepp. 305 - 310
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R3-3
TitleA Two-Step BIST Scheme for Operational Amplifier
Author*Jun Yuan, Masayoshi Tachibana (Kochi Univ. of Tech., Japan)
Pagepp. 311 - 316
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R3-4s
TitleCircuit Partitioning Methods for FPGA-based ASIC Emulator using High-speed Serial Wires
Author*Katsunori Takahashi, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ., Japan)
Pagepp. 317 - 318
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R3-5
TitleTiming-aware Description Methods and Gate-level Simulation of Single Flux Quantum Logic Circuits
Author*Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ., Japan)
Pagepp. 319 - 324
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R3-6
TitleDesign and Analysis of Via-Configurable Routing Fabrics for Structured ASICs
AuthorHsin-Pei Tsai, *Rung-Bin Lin, Liang-Chi Lai (Yuan Ze Univ., Taiwan)
Pagepp. 325 - 329
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R3-7
TitleDevice-level Simulations of Parasitic Bipolar Mechanisim on Preventing MCUs of Redundant Filp-Flops
Author*Kuiyuan Zhang, Ryosuke Yamamoto, Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan)
Pagepp. 330 - 333
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R3-8
TitleA Method of Analog IC Placement with Common Centroid Constraints
Author*Keitaro Ue, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan)
Pagepp. 334 - 339
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R3-9
TitleGPU-based Line Probing Techniques for Mikami Routing Algorithm
Author*Chiu-Yi Chan (Yuan Ze Univ., Taiwan), Jiun-Li Lin (National Cheng Kung Univ., Taiwan), Lung-Sheng Chien (National Tsing Hua Univ., Taiwan), Tsung-Yi Ho (National Cheng Kung Univ., Taiwan), Yi-Yu Liu (Yuan Ze Univ., Taiwan)
Pagepp. 340 - 344
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R3-10
TitleTopology Design for Power Delivery in 3-D Integrated Circuits
Author*Shu-Han Wei, Yi-Hsuan Lee, Chih-Ting Sun, Yu-Min Lee (National Chiao Tung Univ., Taiwan), Liang-Chia Cheng (ITRI, Taiwan)
Pagepp. 345 - 350
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R3-11
TitleA Spur-Reduction Frequency Synthesizer For Wireless Application
Author*Te-Wen Liao, Jun-Ren Su, Chung-Chih Hung (National Chiao Tung Univ., Taiwan)
Pagepp. 351 - 354
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R3-12
TitleDefinite Feature of Low-Energy Operation of Scaled Cross-Current Tetrode (XCT) SOI CMOS Circuits
Author*Yasuhisa Omura, Daishi Ino (Kansai Univ., Japan)
Pagepp. 355 - 360
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R3-13
TitleA Matching Method for Look-ahead Assertion on Pattern Independent Regular Expression Matching Engine
Author*Yoichi Wakaba, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ., Japan)
Pagepp. 361 - 366
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R3-14
TitleHighly-parallel AES Processing for Five Confidentiality Modes with Massive-Parallel SIMD Matrix Processor
Author*Hiroki Yoshikawa, Takeshi Kumaki, Takeshi Fujino (Ritsumeikan Univ., Japan)
Pagepp. 367 - 371
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R3-15
TitleA Trace-Back Method with Source States and its Application to Viterbi Decoders of Low Power and Short Latency
Author*Kazuhito Ito (Saitama Univ., Japan)
Pagepp. 372 - 377
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R3-16
TitleEvaluation of Migration Methods for Island Based Parallel Genetic Algorithm on CUDA
Author*Yuri Ardila, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Pagepp. 378 - 383
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R3-17
TitleFPGA Design of User Monitoring System for Display Power Control
Author*Tomoaki Ando, Vasily Moshnyaga (Fukuoka Univ., Japan)
Pagepp. 384 - 389
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R3-18
TitleA Debug Solution with Synchronizer for CDC
Author*Akitoshi Matsuda (Kyushu Univ., Japan), Shinichi Baba (Kyushu Embedded Forum, Japan)
Pagepp. 390 - 393
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R3-19s
TitleA Low Power-Delay Product Processor Using Multi-valued Decision Diagram Machine
Author*Hiroki Nakahara (Kagoshima Univ., Japan), Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech., Japan)
Pagepp. 394 - 395
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R3-20
TitleA TMR-based Soft Error Mitigation Technique With Less Area Overhead in High-Level Synthesis
AuthorDaiki Tsuruta, *Masayuki Wakizaka, Yuko Hara-Azumi, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Pagepp. 396 - 401
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R3-21
TitlePipeline Circuit Synthesis from C Descriptions for Fast Memory Access in System LSI
Author*Yu-ichi Kitamura (Kinki Univ., Japan), Kazuya Kishida (Panasonic Industrial Devices S&T, Japan), Takashi Kambe (Kinki Univ., Japan)
Pagepp. 402 - 407
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R3-22
TitleA PE-based Pipelining and Assignment Algorithm for Coarse Grained Dynamic Reconfigurable Circuits
Author*Nobuyuki Araki, Takashi Kambe (Kinki Univ., Japan)
Pagepp. 408 - 413
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R3-23
TitleHigh-Level Synthesis Using Partially-Programmable Resources for Yield Improvement
Author*Yuko Hara-Azumi (Univ. of California, Irvine, U.S.A.), Hiroyuki Tomiyama, Shigeru Yamashita (Ritsumeikan Univ., Japan), Nikil D. Dutt (Univ. of California, Irvine, U.S.A.)
Pagepp. 414 - 419
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R3-24
TitleA Method of Power Supply Voltage Assignment and Scheduling of Operations to Reduce Energy Consumption of Error Detectable Computations
Author*Yuki Suda, Kazuhito Ito (Saitama Univ., Japan)
Pagepp. 420 - 424
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R3-25
TitleSoftware Design Methodology based on Energy Consumption Model Considering Relationship between Software and Hardware
Author*Koji Kurihara, Hiromasa Yamauchi, Toshiya Otomo, Takahisa Suzuki (Fujitsu Laboratories Ltd., Japan), Yuta Teranishi (Fujitsu Kyushu Network Technologies Ltd., Japan), Koichiro Yamashita (Fujitsu Laboratories Ltd., Japan)
Pagepp. 425 - 430
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R3-26
TitleElectro-Thermal Modeling and Reliability Simulation of Power MOSFETs with SystemC-AMS - Case Study: An Unclamped Inductive Switching Test Circuit
Author*Keiji Nakabayashi, Takahiro Ozasa (Keirex Technology Inc., Japan), Tamiyo Nakabayashi (Nara Women's Univ., Japan)
Pagepp. 431 - 436
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