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SASIMI 2013
The 18th Workshop on Synthesis And System Integration of Mixed Information Technologies

Poster II
Time: 14:40 - 15:50 Monday, October 21, 2013
Location: Tanchō-Hakuchō 1 & Kujyaku
Chairs: Kenshu Seto (Tokyo City Univ., Japan), Hiroshi Saito (Univ. of Aizu, Japan)

R2-1 (Time: 14:40 - 14:42)
TitlePlace-and-Route Algorithms for a Reliability-Oriented Coarse-Grained Reconfigurable Architecture Using Time Redundancy
Author*Takashi Imagawa, Masayuki Hiromoto (Kyoto Univ., Japan), Hiroshi Tsutsui (Hokkaido Univ., Japan), Hiroyuki Ochi (Ritsumeikan Univ., Japan), Takashi Sato (Kyoto Univ., Japan)
Pagepp. 76 - 81
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R2-2 (Time: 14:42 - 14:44)
TitlePower Analysis Resistant IP Core Using IO-Masked Dual-Rail ROM for Easy Implementation into Low-Power Area-Efficient Cryptographic LSIs
Author*Megumi Shibatani, Mitsuru Shiozaki, Yuki Hashimoto, Takaya Kubota, Takeshi Fujino (Ritsumeikan Univ., Japan)
Pagepp. 82 - 87
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R2-3 (Time: 14:44 - 14:46)
TitleScaling up Size and Number of Expressions in Random Testing of Arithmetic Optimization of C Compilers
AuthorEriko Nagai (Fujitsu Systems West, Japan), *Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
Pagepp. 88 - 93
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R2-4 (Time: 14:46 - 14:48)
TitleA Routing Method Using Minimum Cost Flow Algorithm for Routes with Target Wire Lengths
Author*Kunihiro Fujiyoshi, Kazuo Yamane (Tokyo Univ. of Agri. and Tech., Japan)
Pagepp. 94 - 99
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R2-5 (Time: 14:48 - 14:50)
TitleCompact Pipeline Hardware Architecture for Pattern Matching on Real-Time Traffic Signs Detection
Author*Anh-Tuan Hoang, Mutsumi Omori, Masaharu Yamamoto, Tetsushi Koide (Hiroshima Univ., Japan)
Pagepp. 100 - 105
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R2-6 (Time: 14:50 - 14:52)
TitleA Parallel Simulated Annealing Algorithm with Look-Ahead Neighbor Solution Generation
Author*Yusuke Ota, Kazuhito Ito (Saitama Univ., Japan)
Pagepp. 106 - 111
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R2-7s (Time: 14:52 - 14:54)
TitleA 10-Bit Low-Glitch Binary-Weighted Current-Steering DAC
Author*Fang-Ting Chou, Chung-Chih Hung (National Chiao Tung Univ., Taiwan)
Pagepp. 112 - 113
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R2-8 (Time: 14:54 - 14:56)
TitleRover II: A Router for Via Configurable Structured ASIC with Standard Cells and IPs
AuthorChiung-Chih Ho, Hsin-Pei Tsai, *Rung-Bin Lin (Yuan Ze Univ., Taiwan)
Pagepp. 114 - 117
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R2-9 (Time: 14:56 - 14:58)
TitleA Compact and Energy-Efficient Muller C-Element for Low-Voltage Asynchronous CMOS Digital Circuits
Author*Yuzuru Shizuku, Tetsuya Hirose, Yuya Danno, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 118 - 122
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R2-10 (Time: 14:58 - 15:00)
TitleAnalytical Thermal Modeling and Calibration Method for Lithium-Ion Batteries
Author*Keiji Kato, Yusuke Yamamoto, Naoki Kawarabayashi, Lei Lin, Masahiro Fukui (Ritsumeikan Univ., Japan)
Pagepp. 123 - 128
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R2-11 (Time: 15:00 - 15:02)
TitleA Sensor Modeling Technique Using SystemC-AMS For Fast Simulation of System-in-Package Based Bio-Medical Systems
Author*Arif Ullah Khan, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Pagepp. 129 - 133
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R2-12 (Time: 15:02 - 15:04)
TitleA Cool Charger for Lithium-Ion Battery
Author*Yusuke Yamamoto, Keiji Kato, Lei Lin, Masahiro Fukui (Ritsumeikan Univ., Japan)
Pagepp. 134 - 139
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R2-13s (Time: 15:04 - 15:06)
TitleA Hardware Generator for Aesthetic Nonlinear Filter Banks
Author*Tomoki Komuro, Hirotaka Nishikawa, Yukihiro Iguchi, Kaoru Arakawa (Meiji Univ., Japan)
Pagepp. 140 - 141
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