| Title | Fast Transient and High Current Efficiency Voltage Regulator with Hybrid Dynamic Biasing Technique |
| Author | Chia-Min Chen, *Yen-Wei Liu, Chung-Chih Hung (National Chiao Tung University, Taiwan) |
| Page | pp. 119 - 122 |
| Keyword | Capacitive coupling, voltage spike, low-dropout regulator, hybrid dynamic biasing, transient response |
| Abstract | This paper presents an output-capacitorless low-dropout (LDO) voltage regulator that achieves fast transient responses by hybrid dynamic biasing. The hybrid dynamic biasing in the proposed transient improvement circuit is activated through capacitive coupling. The proposed transient improvement circuit senses the LDO output change so as to increase the bias current instantly. The proposed circuit was applied to an output-capacitorless LDO implemented in standard 0.35-um CMOS technology. The device consumes only 25 uA of quiescent current with a dropout voltage of 180 mV. The proposed circuit reduces the output voltage spike of the LDO to 80 mV when the output current is changed from 0 mA to 100 mA. The output voltage spike is reduced to 20 mV when the supply voltage varies between 1.3 V and 2.3 V with a load current of 100 mA. |
| Title | Scan Test of Latch-Based Asynchronous Pipeline Circuits under 2-Phase Handshaking Protocol |
| Author | *Kyohei Terayama, Atsushi Kurokawa, Masashi Imai (Hirosaki University, Japan) |
| Page | pp. 128 - 133 |
| Keyword | test, asynchronous circuit, scan D-latch, 2phase handshaking protocol |
| Abstract | Asynchronous MOUSETRAP pipeline circuit is a simple and fast circuit thanks to the 2-phase handshaking protocol which has no return-to-zero overhead. In this paper, we propose two scan D-latches in order to support its scan test since D-latches are used instead of flip-flops in the MOUSETRAP. We design some MOUSETRAP pipeline circuits with the ISCAS89 benchmark combinational circuits using 130nm process technologies and show some evaluation results of the overhead and the fault coverage under the single stuck-at fault model. |
| PDF file |
| Title | Data Reduction and Parallelization for Human Detection System |
| Author | *Mao Hatto, Takaaki Miyajima, Hideharu Amano (Keio University, Japan) |
| Page | pp. 134 - 139 |
| Keyword | Human Detection, FPGA, parallelization, data reduction, HW/SW Co-design |
| Abstract | HOG (Histogram of Oriented Gradients) is one of the effective
ways for extracting feature values. Also, Real Adaboost
algorithm has high recognition ratio, and it is adequate to
hardware implementation. Many researches on human detection
systems adopted these two algorithms and had achieved
progress. However, data volume of HOG feature is still a
problem in the whole system. Data volume from only one
frame could be over 1 GB, and this data volume causes some
difficulties from the view point of both sending data to a server
and execution speed. Especially, since much data volume
presses also internal data communication between modules in
hardware execution, much data volume could be a bottle-neck
of the whole system operating speed.
Here, a high speed and small memory consuming implementation
of human detection system using Hardware-Software
Co-design is proposed. For the executing speed of the system,
HOG feature values are accelerated by an FPGA, and Real
Adaboost detection is executed only by accessing ROM data
in the FPGA. As a result, HOG+Real Adaboost part was
accelerated about 23.1 times faster compared to the software
execution. Whole system had been implemented on a single
board, and it achieved 3.22 times speed up from camera input
to VGA display output. Also we tried to reduce feature data
volume, and achieved 93.75% of data compression compared
to double precision calculation, with only 2.68% loss of the
recognition accuracy. |
| PDF file |
| Title | Evaluation of Approximate SAD Circuits with Error Compensation |
| Author | *Toshihiro Goto, Yasunori Takagi, Shigeru Yamashita (Ritsumeikan University, Japan) |
| Page | pp. 140 - 145 |
| Keyword | SAD, approximate comupting |
| Abstract | This paper proposes and evaluates an “approximate” but fast Sum of Absolute Difference (SAD) circuit to provide a design experience for approximate computing, which is an emerging research area. Our idea to design an “approximate” but fast circuit is similar to the one in the previous works in approximate computing researches. Unlike the previous works, we also propose various error compensation methods to use the circuit for real applications. Moreover, this paper reports the result of our hardware design, and our software evaluation of our various error compensation methods by using video compression applications. Our results show that our SAD circuit (with some errors) can reduce the total processing time by 10.71% than the conventional SAD circuit (without error), although it can provide acceptable quality for the video compression applications. |
| Title | A Circuit Implementable 5-Output nMOSFET Shearing Stress Sensor |
| Author | *Tomochika Harada, Kousuke Takeuchi (Yamagata University, Japan) |
| Page | pp. 146 - 148 |
| Keyword | shearing stress sensor, MOSFET sensor, multi-output sensor |
| Abstract | In this paper, we design, fabricate, and evaluate stress detection operation of 5-output MOSFET type stress detection element. We can verify in strong inversion regions. Stress detection sensitivity can be changed by VGS in the saturation region. If VGS is constant, stress detection sensitivity must set to constant. Furthermore, stress sensitivity is variable by VDS (Not VGS) in the linear region. |
| Title | Iddq Testing Against Process Variations and Measurement Noises |
| Author | Chia-Ling Chang, *Jack Sheng-Yan Lin, Clarles Hung-Pin Wen (National Chiao Tung University, Taiwan) |
| Page | pp. 149 - 150 |
| Keyword | Iddq, Data mining, process variation |
| Abstract | Analyzing test data can have a significant impact on improving production test and parametric yield. The work investigates the test data analysis on Iddq test data to extract certain knowledge to estimate the process parameters and screen potential defective chips. With a simulation framework, we demonstrate the dependency of this screening to various assumptions, such as the amount of process variations, the sensitivity of measurement noises and the number of Iddq patterns. Experimental results on IWLS’05 designs show that the Iddq analysis reveals its strengths on screening faulty samples under various variations and assumptions in a 45nm technology. |
| Title | Pre-Bond Interposer Test Methodology for System in Package |
| Author | Katherine Shu-Min Li (Department of Computer Science, National Sun Yat-sen University, Taiwan), Sying-Jyan Wang (Department of Computer Science, National Chung Hsing University, Taiwan), Cheng-You Ho (Department of Computer Science, National Sun Yat-sen University, Taiwan), Yingchieh Ho (Department of Electrical Engineering, National Dong Hwa University, Taiwan), Ruei-Ting Gu (National Sun Yat-sen University/Advanced Semiconductor Engineering (ASE) Group, Taiwan), Bo-Chuan Cheng (Advanced Semiconductor Engineering (ASE) Group, Taiwan) |
| Page | pp. 151 - 156 |
| Keyword | interposer, test, 2.5D, System in Package, Through-Silicon-Via |
| Abstract | Pre-bond testing of silicon interposer is difficult due
to the large number of nets to be tested and small number of
test access ports. Recently, it was proposed to include a test
interposer that is contacted with the interposer under test in
the testing process. Combining these two interposers provides
access to nets that are not normally accessible. Previous
synthesis method for test interposer was based on constrained
breadth-first search, which can be time-consuming. Besides,
separate test interposers have to be provided for open and
short fault testing. In this paper, we present a theoretical study
on the topology of testable circuit structure for interconnect
faults in silicon interposer. Based on the theoretical framework,
a more efficient synthesis method is developed. Furthermore, a
single test interposer can be used for both open and short fault
detection, which leads to shorter test time and lower test cost. |
| Title | Oxygen Sensor Module with Majority Sensing for Monitoring Wide Area at Disaster |
| Author | *Ryuta Nishino, Tatsuya Yamada, Qing Dong, Shigetoshi Nakatake (The University of Kitakyushu, Japan) |
| Page | pp. 157 - 158 |
| Keyword | Sensor, Majority Sensing, Oxygen Concentration |
| Abstract | This work presents a new sensor module with majority sensing which improve an accuracy by multiple sensor devices. The sensor modules are distributed over disaster region for monitoring environmental information such as a temperature of the surface and oxygen concentration. Each sensor module is connected by a wireless network and transmits the information to a monitoring server. In this work, we focus on sensing oxygen concentration in case of forest fire. To improve an accuracy of the sensing value, we introduce a new sensing mechanism called majority sensing with multiple sensor devices. In experiments, we demonstrate 8.4-14% improvement for the oxygen concentration sensing. |
| PDF file |
| Title | FPGA Implementation and Evaluation of Image Scaling Circuits Using Seletor-Logic-Based Bi-Linear Interpolation |
| Author | *Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda University, Japan) |
| Page | pp. 159 - 160 |
| Keyword | selector logic, FPGA, bi-linear interpolation |
| Abstract | Bi-linear interpolation is one of interpolation techniques, which interpolates a pixel value linearly from its four circumferences and often used for image scaling. In this paper, we pick up a method to interpolate pixels using selector logics and implement and evaluate it on an FPGA board. By applying selector logics to a bi-Linear interpolation operation, its total product terms are decreased and thus a circuit size and circuit delay are improved. We realize approximately 15.7% speed-up using selector-logic-based bi-linear interpolation. |
| Title | An Accelerator for Frequent Itemset Mining from Data Stream with Parallel Item Tree |
| Author | *Kasho Yamamoto, Tsunaki Sadahisa, Dahoo Kim, Eric S. Fukuda, Tetsuya Asai, Masato Motomura (Hokkaido University, Japan) |
| Page | pp. 161 - 162 |
| Keyword | data mining, frequent itemsets, stream processing, hardware accelerator |
| Abstract | Frequent itemset mining attempts to find frequent subsets in a transaction database. In this era of big data, demand for frequent itemset mining is increasing. Therefore, the combination of fast implementation and low memory consumption, especially for stream data, is needed. In response to this, we optimize an online algorithm, called Skip LC-SS algorithm, for hardware.In this paper, we present an efficient architecture based on this algorithm. |
| Title | A Leakage Current Reduction Algorithm Using Input Vector Control and Cell Topology Modification |
| Author | Tsung-Yi Wu (National Changhua University of Education, Taiwan), Hsin-Hui Li (Global Unichip Corp., Taiwan), *Zhi-Yao Ding, Guan-Cheng Guo (National Changhua University of Education, Taiwan) |
| Page | pp. 163 - 164 |
| Keyword | cell topology modification, input vector control, leakage current reduction, sleep mode |
| Abstract | Since the leakage current of a digital circuit depends on the states of its logic gates, assigning a minimum leakage vector to its primary inputs in the sleep mode is a feasible technique for leakage current reduction. In this paper, we propose a heuristic algorithm that applies a cell topology modification and pin reordering technique and minimum leakage vector assignment for leakage current reduction. Experimental results show that the algorithm can reduce the leakage current by average 11.8%. |
| Title | Majority-Inverter Graph for FPGA Synthesis |
| Author | *Luca Amaru (EPFL - LSI, Switzerland), Ana Petkovska (EPFL - LAP, Switzerland), Pierre-Emmanuel Gaillardon (EPFL - LSI, Switzerland), David Novo Bruna, Paolo Ienne (EPFL - LAP, Switzerland), Giovanni De Micheli (EPFL - LSI, Switzerland) |
| Page | pp. 165 - 170 |
| Keyword | Majority-Inverter Graph, Logic Synthesis, FPGA |
| Abstract | In this paper, we present an FPGA synthesis flow based on Majority-Inverter Graph (MIG). An MIG is a directed acyclic graph consisting of three-input majority nodes and regular/complemented edges. MIG manipulation is supported by a consistent algebraic framework leading to strong synthesis properties. We propose MIG optimization techniques targeting high-speed FPGA implementations. For this purpose, we reduce the depth of logic circuits via MIG algebraic transformations enabling denser LUT mapping on FPGAs. Experimental results show that our MIG-based design flow reduces by 21%, on average, the delay of the arithmetic circuits synthesized on a state-of-art 28nm commercial FPGA device, as compared to a commercial design flow. |
| PDF file |
| Title | High Observability Scan Chains with Improving Output Compaction Efficiency |
| Author | Sying-Jyan Wang, Che-Wei Kao (Department of Computer Science and Engineering, National Chung Hsing University, Taiwan), Katherine Shu-Min Li (Department of Computer Science and Engineering, National Sun Yat-sen University, Taiwan) |
| Page | pp. 171 - 176 |
| Keyword | scan test, scan chain, output compaction, X-tolerance, diagnosability |
| Abstract | Output selection is recently proposed for test
response compaction. This scheme achieves zero aliasing, full
X-tolerance, and high diagnosability, at the cost of inflated test
set and non-trivial hardware overhead. The time/space penalty
in test output compaction is mainly attributed to the loss of
observability. In previous methods, it was in general assumed
that erroneous responses are uniformly distributed among all
scan chains, and the output compactors are designed
accordingly. In this paper, we present three techniques to
improve the performance of output selection based test
response compaction. (1) The uneven distribution of erroneous
test responses is exploited to optimize compactor design. (2) A
test dynamic compaction algorithm is provided to deal with the
test set inflation problem. (3) A low-cost test response
compactor is presented. Experimental results indicate that the
proposed techniques can achieve better compaction results
with lower hardware overhead. |
| Title | Using Structural Relations for Checking Combinationality of Cyclic Circuits |
| Author | Wan-Chen Weng (National Tsing Hua University, Taiwan), Yung-Chih Chen (Yuan Ze University, Taiwan), Jui-Hung Chen, *Ching-Yi Huang, Chun-Yao Wang (National Tsing Hua University, Taiwan) |
| Page | pp. 177 - 182 |
| Keyword | combinationality, cyclic circuit |
| Abstract | Functionality and combinationality are two main issues that have to be dealt with in cyclic combinational circuits, which are combinational circuits containing loops. Cyclic circuits are combinational if nodes within the circuits are definite values under all input assignments. For a cyclified circuit, we have to check whether it is combinational or not. Thus, this paper proposes an efficient two-stage algorithm to verify the combinationality of cyclic circuits. A set of cyclified IWLS 2005 benchmarks are performed to demonstrate the efficiency of the proposed algorithm. Compared to the state-of-the-art algorithm, our approach has a speedup of about 4000 times on average. |
| Title | YAPSIM: Yet Another Parallel Logic Simulation Using GP-GPU |
| Author | *Takuya Hashiguchi, Yuichiro Mori, Masahiko Toyonaga, Michiaki Muraoka (Kochi University, Japan) |
| Page | pp. 183 - 186 |
| Keyword | GP-GPU, Logic Simulator, Parallel algorithm |
| Abstract | In this paper, a new high-speed logic simulator YAPSIM based on a parallel logic simulation methodology using GP-GPU is presented. It consists of three acceleration methods for simulation performance, a fan-out cone grouping method, a LUT method and a GPU internal memory access method. The experimental comparison result shows that YAPSIM executed 29 times faster than a high speed commercial simulator for a combinational circuit of 75,000 gates, and 5.7 times faster for a sequential circuit of 84,000 gates respectively. |
| PDF file |
| Title | Technology Mapping Method for Low Power Consumption and High Performance in General-Synchronous Framework |
| Author | *Junki Kawaguchi, Yukihide Kohira (The University of Aizu, Japan) |
| Page | pp. 187 - 192 |
| Keyword | General-Synchronous Framework, Technology Mapping, Integer Linear Programming |
| Abstract | In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, circuit performance is expected to be improved compared to complete-synchronous framework, in which the clock is distributed periodically and simultaneously to each register. To improve the circuit performance more, logic circuit synthesis for general-synchronous framework is required. In this paper, under the assumption that any clock schedule is realized by an ideal clock distribution circuit, when two or more cell libraries are available, a technology mapping method which assigns a cell to each gate in the given logic circuit by using integer linear programming is proposed. In experiments, we show the effectiveness of the proposed technology mapping method. |
| PDF file |
| Title | A Quaternary Master-Slave Flip-Flop with Multiple Functions for Multi-Valued Logics |
| Author | *Renyuan Zhang, Mineo Kaneko (Japan Advanced Institute of Science and Technology, Japan) |
| Page | pp. 193 - 198 |
| Keyword | quaternary, flip-flop, Neuron-MOS |
| Abstract | A prototype of flip-flop circuit is proposed in this work for storing quaternary signals. Inspired by the Neuron-MOS mechanism, the capacitance-coupling technology is implemented to realize multi-threshold inverters. On the basis of this technology, a self-lock feedback scheme is proposed to process and store quaternary signals with standard CMOS technology and ordinary dual-rail supply voltage. Thanks to the inherent property of quaternary processing and proposed scheme, various behaviors can be easily achieved without additional combination-circuits. An example is given on the quaternary counter with sixteen states. From circuit simulation results, the proposed quaternary multi-functional flip-flop achieves all the basic and extended functions correctly. |
| PDF file |
| Title | Quantitative Evaluations and Efficient Exploration for Optimal Partially-Programmable Circuits Generation |
| Author | *Takumi Tsuzuki (Nara Institute of Science and Technology, Japan), Yuko Hara-Azumi (Tokyo Institute of Technology, Japan), Shigeru Yamashita (Ritsumeikan University, Japan), Yasuhiko Nakashima (Nara Institute of Science and Technology, Japan) |
| Page | pp. 199 - 204 |
| Keyword | fault tolerance, PPC(Partially-Programmable Circuits), LUT(Look Up Tabble) |
| Abstract | In this paper, based on Partially-Programmable Circuits (PPCs), which have been recently proposed for improving the fault tolerance of circuits, we study further effective PPC generation by exploring wider design space. First, we quantitatively evaluated various aspects which may affect the fault tolerance of PPC. Exploiting the findings obtained, we then successfully generated PPCs which improve the area-efficiency of fault tolerance by 34% compared with an existing PPC generation method. Moreover, we developed an efficient exploration of PPCs, leading to exploration time reduction by 70% over exhaustive search, without affecting the optimality. |