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The 15th Workshop on Synthesis And System Integration of Mixed Information technologies

Poster I: Low Power and Timing
Time: 10:00 - 11:45 Monday, March 9, 2009
Location: Waikele & Kaneohe
Chairs: Jimmy Chien-Nan Liu (National Central Univ., Taiwan), Hiroaki Yoshida (Univ. of Tokyo, Japan)

R1-1 (Time: 10:00 - 10:03)
TitleA New RTL Power Macro-modeling and Efficient Power Estimation Scheme
Author*Masaaki Ohtsuki, Masato Kawai, Masahiro Fukui (Ritsumeikan Univ., Japan)
Pagepp. 11 - 16
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R1-2 (Time: 10:03 - 10:06)
TitleAn Efficient Hardware Circuit Simulator for Power Grid Optimization System
Author*Taiki Hashizume, Shinichi Nishizawa, Hisako Sugano (Ritsumeikan Univ., Japan), Masaya Yoshikawa (Meijo Univ., Japan), Masahiro Fukui (Ritsumeikan Univ., Japan)
Pagepp. 17 - 22
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R1-3 (Time: 10:06 - 10:09)
TitleIR-Drop-Aware Buffer/Flip-Flop Station Planning in Floorplan Design
AuthorHsin-Hwa Pan (AnaGlobe Technology, Inc., Taiwan), *Hung-Ming Chen (National Chiao Tung Univ., Taiwan), Chia-Yi Chang (Realtek Semiconductor Corp., Taiwan)
Pagepp. 23 - 28
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R1-4 (Time: 10:09 - 10:12)
TitleIR Drop-Driven Algorithm for Standard Cell Placement Considering Timing Windows
Author*Naoki Kitamura, Nobuyuki Umakoshi, Kaoru Okazaki (Osaka Electro-Communication Univ., Japan), Masayuki Terai (Osaka Gakuin Univ., Japan)
Pagepp. 29 - 34
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R1-5 (Time: 10:12 - 10:15)
TitleEnergy Dissipation Reduction of Arithmetic Operations with Valid Digits
Author*Kazuhito Ito, Yorito Nagasaka (Saitama Univ., Japan)
Pagepp. 35 - 40
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R1-6 (Time: 10:15 - 10:18)
TitlePower Efficiency Index for Low Power LSI Design
Author*Yutaka Tamiya (Fujitsu Laboratories Ltd., Japan), Masahiro Fujita (Univ. of Tokyo, Japan)
Pagepp. 41 - 46
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R1-7 (Time: 10:18 - 10:21)
TitleA Microprocessor-based Architecture for a Smart in vivo Biosensor
Author*Yohei Fukumizu, Tomonori Izumi, Hironori Yamauchi (Ritsumeikan Univ., Japan)
Pagepp. 47 - 51
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R1-8 (Time: 10:21 - 10:24)
TitleLow Power Unequal Error Protection Media System Based on Error Concealment in H.264/AVC
Author*Yichun Tang, Jun Wang, Naoki Tajima, Satoshi Goto (Waseda Univ., Japan)
Pagepp. 52 - 57
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R1-9 (Time: 10:24 - 10:27)
TitleAn Experimental Comparison of Power Analysis Attacks against RSA Processors on ASIC and FPGA
Author*Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki (Tohoku Univ., Japan), Akashi Satoh (AIST, Japan)
Pagepp. 58 - 63
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R1-10 (Time: 10:27 - 10:30)
TitleOn Using Spare Cells for Functional Changes with Wirelength Consideration
Author*Yun-Ru Wu, Shu-Yun Chen (Realtek Semiconductor Crop., Taiwan), Kuang-Yao Lee, Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Pagepp. 64 - 69
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R1-11 (Time: 10:30 - 10:33)
TitleA Gaussian Mixture Model to Propagate Delay and Slew Distributions Together in Statistical Timing Analysis
Author*Shingo Takahashi, Shuji Tsukiyama (Chuo Univ., Japan)
Pagepp. 70 - 75
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R1-12 (Time: 10:33 - 10:36)
TitleEmbedded Delay Detectors to Choose the Fastest Route in FPGAs for Variation-aware Reconfiguration
Author*Yohei Kume, Yuuri Sugihara, Camlai Ngo, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ., Japan)
Pagepp. 76 - 81
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R1-13 (Time: 10:36 - 10:39)
TitlePerformance-Driven Architectural Synthesis for Multicycle Communication
Author*Chia-I Chen, Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Pagepp. 82 - 87
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R1-14 (Time: 10:39 - 10:42)
TitleA Fast Regular Expression Matching Engine for an FPGA-based Network Intrusion Detection System
Author*Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ., Japan)
Pagepp. 88 - 93
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R1-15 (Time: 10:42 - 10:45)
TitleFast Division Circuit in GF(2m) Based on the Extended Euclid's Algorithm with Parallelization of Modular Reductions
Author*Katsuki Kobayashi, Naofumi Takagi (Nagoya Univ., Japan)
Pagepp. 94 - 99
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