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The 15th Workshop on Synthesis And System Integration of Mixed Information technologies

Poster II: System Algorithm and Design
Time: 14:15 - 16:00 Monday, March 9, 2009
Location: Manza & Kaneohe
Chairs: Juinn-Dar Huang (National Chiao Tung Univ., Taiwan), Kazuhito Ito (Saitama Univ., Japan)

R2-1 (Time: 14:15 - 14:18)
TitleStatic Scheduling of Dynamic Execution for High-Level Synthesis
Author*Yuki Toda, Nagisa Ishiura, Kousuke Sone (Kwansei Gakuin Univ., Japan)
Pagepp. 107 - 112
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R2-2 (Time: 14:18 - 14:21)
TitleTRANSYSCTOR: A General Methodology and Framework for Rule-Based Transformation and Refactoring of SystemC Designs
Author*Alexander Viehl, Jordan Dukadinov, Oliver Bringmann (FZI Forschungszentrum Informatik, Germany), Wolfgang Rosenstiel (Univ. of Tübingen, Germany)
Pagepp. 113 - 118
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R2-3 (Time: 14:21 - 14:24)
TitleAn Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits
Author*Kosuke Shioki, Narumi Okada, Toshiro Ishihara, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 119 - 124
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R2-4 (Time: 14:24 - 14:27)
TitleAn Efficient Exploring Method of Room-to-Room Floorplan
Author*Yosuke Takahashi, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan)
Pagepp. 125 - 130
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R2-5 (Time: 14:27 - 14:30)
TitleA Conjecture on the Number of Extra Registers in Safe Clocking-Based Register Assignment
Author*Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST, Japan)
Pagepp. 131 - 136
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R2-6 (Time: 14:30 - 14:33)
TitleCircuit Acyclic Clustering with Input/Output Constraints and Applications
Author*Rung-Bin Lin, Tsung-Han Lin, Shin-An Wu (Yuan Ze Univ., Taiwan)
Pagepp. 137 - 142
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R2-7 (Time: 14:33 - 14:36)
TitleOn the Number of Rooms in a Rectangular Solid Dissection
Author*Hidenori Ohta (Tokyo Univ. of Agri. and Tech., Japan), Toshinori Yamada (Saitama Univ., Japan), Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan)
Pagepp. 143 - 148
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R2-8 (Time: 14:36 - 14:39)
TitleAssertion Checker Synthesis for FPGA Emulation
Author*Chengjie Zang, Qixin Wei, Shinji Kimura (Waseda Univ., Japan)
Pagepp. 149 - 154
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R2-9 (Time: 14:39 - 14:42)
TitleAutomatic Pipeline Generation for FPGA-based Prototyping
Author*Weijie Xing, Kai Zheng (Waseda Univ., Japan), Tomoo Kimura, Shunichi Kuromaru, Kouji Kai (Panasonic Corp., Japan), Shinji Kimura (Waseda Univ., Japan)
Pagepp. 155 - 160
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R2-10 (Time: 14:42 - 14:45)
TitleVLSI Design of a Handwritten-Character Learning and Recognition system based on Associative Memory
Author*Shogo Sakakibara, Wataru Imafuku, Akio Kawabata, Tania Ansari, Hans Jürgen Mattausch, Tetsushi Koide (Hiroshima Univ., Japan)
Pagepp. 161 - 166
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R2-11 (Time: 14:45 - 14:48)
TitleImproved Region-Growing Image-Segmentation Algorithm Based on the HSV Color Space
Author*Tatsuya Sugahara, Keita Okazaki, Naomi Nagaoka, Ryosuke Kimura, Tetsushi Koide, Hans Jürgen Mattausch (Hiroshima Univ., Japan)
Pagepp. 167 - 171
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R2-12 (Time: 14:48 - 14:51)
TitleThe Design of Frequency Domain Inter Carrier Interference (ICI) Canceling Circuit caused by Radio Frequency Shift for OFDM Receiver
Author*Kenta Nohara, Tomohisa Wada (Univ. of the Ryukyus, Japan)
Pagepp. 172 - 176
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R2-13 (Time: 14:51 - 14:54)
TitleA New Architecture Extension for Mitigation of Permanent Functional Unit Faults Using Hot-Swapping Concepts
Author*Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroyuki Ochi (Kyoto Univ., Japan), Yukihiro Nakamura (Ritsumeikan Univ., Japan)
Pagepp. 177 - 182
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R2-14 (Time: 14:54 - 14:57)
TitleA Bottom-Up Exploration Approach for 3D Graphics Hardware Accelerator in Consumer Electronics
Author*Chi-Tsai Yeh, Liang-Bi Chen, Ching-Yuan Lin, Hung-Yu Chen, Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)
Pagepp. 183 - 188
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R2-15 (Time: 14:57 - 15:00)
TitleSmall Area Multipliers Utilizing the Sum of Operands
Author*Hirotaka Kawashima, Naofumi Takagi (Nagoya Univ., Japan)
Pagepp. 189 - 194
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