| Title | Static Scheduling of Dynamic Execution for High-Level Synthesis |
| Author | *Yuki Toda, Nagisa Ishiura, Kousuke Sone (Kwansei Gakuin University, Japan) |
| Page | pp. 107 - 112 |
| Keyword | high-level synthesis, behavioral synthesis, variable scheduling, indefinite cycle operation |
| Abstract | This article presents variable scheduling and binding for high-level synthesis. Conventional scheduling algorithms decide the operations' execution timing assuming that each operation takes a fixed number of cycles. However, on some operations, the number of cycles may vary depending on the values of operands or the states of the hardware. The variable scheduling enables efficient computation in the presence of such indefinite cycle operations. Experimental results show that the number of the execution cycles are reduced by about 18%. |
| Title | TRANSYSCTOR: A General Methodology and Framework for Rule-Based Transformation and Refactoring of SystemC Designs |
| Author | *Alexander Viehl, Jordan Dukadinov, Oliver Bringmann (FZI Forschungszentrum Informatik, Germany), Wolfgang Rosenstiel (University of Tübingen, Germany) |
| Page | pp. 113 - 118 |
| Keyword | SystemC, Design Automation, Transformation, Verification, Performance analysis |
| Abstract | In this paper, a framework is presented for performing automated transformations of SystemC designs based on transformation rules with the objective of speeding up system design and verification implementation with SystemC. The framework is based on an open source SystemC parser and provides a generic transformation core as well as the ability of C++/SystemC code generation as backend. Two use cases from design verification and formal performance analysis are presented for showing different application areas, flexibility, and extensibility of the developed methodology. Experiments provide promising numbers on saved implementation efforts and hence on the high value of the developed solution. |
| Title | An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits |
| Author | *Kosuke Shioki, Narumi Okada, Toshiro Ishihara, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe University, Japan) |
| Page | pp. 119 - 124 |
| Keyword | Error diagnosis, ECO, Design error, Incremental synthesis |
| Abstract | This paper presents an error diagnosis technique based on location sets to rectify subcircuits. This technique can rectify circuits including LUT function errors by fewer modifications than the conventional technique. The proposed technique obtains sets of the locations for rectifying subcircuits, and rectifies circuits based on the sets. Experimental results have shown that our technique reduces increase in the number of locations to be rectified with conventional technique by 95 %. |
| Title | An Efficient Exploring Method of Room-to-Room Floorplan |
| Author | *Yosuke Takahashi, Kunihiro Fujiyoshi (Tokyo University of Agriculture and Technology, Japan) |
| Page | pp. 125 - 130 |
| Keyword | Floorplan, Adjacency, FT-Squeeze, Simulated Annealing |
| Abstract | A floorplan is often a dissection of a rectangle chip by horizontal and vertical line segments, and decides rough position of modules in the chip. FT-Squeeze, which is a permutation of room numbers and can represent any floorplan, has been proposed. Based on FT-Squeeze, we can search floorplans using Simulated Annealing. But if a constraint that some modules must be assigned to adjacent rooms is imposed, the search takes enormous time since many solutions are found that they violate the constraints after the decoding. In this paper, we propose a method to check whether two appointed modules are assigned to adjacent rooms in constant time. |
| Title | A Conjecture on the Number of Extra Registers in Safe Clocking-Based Register Assignment |
| Author | *Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (Japan Advanced Institute of Science and Technology, Japan) |
| Page | pp. 131 - 136 |
| Keyword | delay variation, register assignment, BDD clocking |
| Abstract | Recently, Backward-Data-Direction (BDD) clocking based register assignment in high-level synthesis has been proposed. However, as a major drawback, BDD clocking based register assignment tends to increase the number of registers. It causes the area overhead and the extra power consumption, therefore it should be minimized. Interestingly, the experiments we have done so far show that the increase is at most one. This paper treats the simple question whether the register overhead is always at most one or not. An estimation of the upper-bound is helpful not only for estimating the number of extra registers when we apply BDD clocking, but also for developing a heuristic algorithm for BDD clocking based register assignment. The conjecture proposed in this paper is not proved nor disproved in general cases. In this paper, we proved and showed that it is true for two simple cases. |
| Title | Circuit Acyclic Clustering with Input/Output Constraints and Applications |
| Author | *Rung-Bin Lin, Tsung-Han Lin, Shin-An Wu (Yuan Ze University, Taiwan) |
| Page | pp. 137 - 142 |
| Keyword | Circuit Clustering, Partitioning, Acyclic, Logic simulation, Leakage power |
| Abstract | This article studies a new circuit acyclic clustering problem which divides a combinational circuit into groups of sub-circuits, each of which has a limited numbers of inputs and outputs. Several heuristics are proposed for solving this problem. With application of our partitioning results, we achieve on average three times speedup on logic simulation for finding an input vector that incurs minimum or maximum leakage power dissipation. Applications of our approach to other area such as physical design are possible. |
| Title | On the Number of Rooms in a Rectangular Solid Dissection |
| Author | *Hidenori Ohta (Tokyo University of Agriculture and Technology, Japan), Toshinori Yamada (Saitama University, Japan), Kunihiro Fujiyoshi (Tokyo University of Agriculture and Technology, Japan) |
| Page | pp. 143 - 148 |
| Keyword | Rectangular Solid Dissection, Rectangular Dissection, 3D-VLSI, Number of Rooms, Plane Graph |
| Abstract | In these years, 3D-LSIs which consist of several silicon layers have been developed and been attracted attentions. For floorplaning of 3D-LSIs, a rectangular solid dissection, which is a dissection of a rectangular solid into smaller rectangular solids by planes, also has been attracted attentions and been studied much. However, not so many properties have been clarified about a rectangular solid dissection. This paper presents the relation between the number of rooms and that of walls in a rectangular solid dissection. |
| Title | Assertion Checker Synthesis for FPGA Emulation |
| Author | *Chengjie Zang, Qixin Wei, Shinji Kimura (Graduate School of Information, Production and Systems, Waseda University, Japan) |
| Page | pp. 149 - 154 |
| Keyword | SystemVerilog Assertion, finite input memory automaton, synthesis, FPGA |
| Abstract | In the paper, we propose a method to synthesize SystemVerilog Assertion checkers for FPGA emulation. The main idea is to synthesize assertions based on finite input memory automata(FIMA) and use embedded RAM modules to construct shift register chain to store the history of variables. The method does not consume logic elements for storing the value and the shift register using the embedded RAM is much more efficient compared with the one uses the registers in logic elements. We also compare proposed FIMA method with MBAC method and a tool of FoCs. |
| Title | Automatic Pipeline Generation for FPGA-based Prototyping |
| Author | *Weijie Xing, Kai Zheng (Graduate School of Information, Production and Systems, Waseda University, Japan), Tomoo Kimura, Shunichi Kuromaru, Kouji Kai (Panasonic Corporation, Japan), Shinji Kimura (Graduate School of Information, Production and Systems, Waseda University, Japan) |
| Page | pp. 155 - 160 |
| Keyword | FPGA, acceleration, pipeline |
| Abstract | In this paper, we propose a new approach for the acceleration of circuits by automatically generating pipeline structures for FPGA-based prototyping. In the method, an original circuit from the FPGA mapping result is converted into a pipelined one by dividing the circuits to several parts using pipeling registers. When introducing pipeline registers, we utilize the un-used registers in logic elements of FPGA. The method divides a combinational part of the original circuit into shorter-delay parts by using the cut-set based algorithm for enhancing the data throughput, and show several sufficient conditions under which circuits can be correctly converted to pipelined ones. The effect of this method is shown by the experimental results using a tool implementing the algorithm |
| Title | VLSI Design of a Handwritten-Character Learning and Recognition system based on Associative Memory |
| Author | *Shogo Sakakibara, Wataru Imafuku, Akio Kawabata, Tania Ansari, Hans Jürgen Mattausch, Tetsushi Koide (Hiroshima University, Japan) |
| Page | pp. 161 - 166 |
| Keyword | Associative Memory, Character Recognition, Learning, Optimization, LSI |
| Abstract | In the presented research, an associative memory architecture for searching the most similar data among previously stored reference data is applied. The chosen associative memory achieves high speed, low power consumption and small implementation area. To recognize new data, a learning capability based on the concept of short/long-term memory is realized. For improvement of the recognition rate, we propose a reference-data-optimization algorithm. We evaluated the proposed VLSI-design method for the application of hand-written character learning and recognition. Test-chip in 0.18 um CMOS technology was designed to demonstrate the proposed algorithm and design method. |
| Title | Improved Region-Growing Image-Segmentation Algorithm Based on the HSV Color Space |
| Author | *Tatsuya Sugahara, Keita Okazaki, Naomi Nagaoka, Ryosuke Kimura, Tetsushi Koide, Hans Jürgen Mattausch (Hiroshima University, Japan) |
| Page | pp. 167 - 171 |
| Keyword | image segmentation, connection-weight, color space |
| Abstract | This paper presents an image-segmentation algorithm which uses a connection-weight-based region-growing algorithm. The calculation of the connection weights, which express the similarity between neighboring pixels, is based on the HSV color space. Two new methods for improvement of segmentation results are applied, namely (i) dynamically changing the classification border between chromatic and achromatic pixels and (ii) 2nd stage segmentation if the Volume color space component has a wide distribution for a segment obtained in the 1st stage segmentation. The effectiveness of these methods for improving the segmentation quality is confirmed with segmentation examples of natural images. } |
| Title | The Design of Frequency Domain Inter Carrier Interference (ICI) Canceling Circuit caused by Radio Frequency Shift for OFDM Receiver |
| Author | *Kenta Nohara, Tomohisa Wada (University of the Ryukyus, Japan) |
| Page | pp. 172 - 176 |
| Keyword | OFDM, ICI, FIR filter, Scatterd pilot, Radio Frequency Shift |
| Abstract | Orthogonal Frequency Division Multiplexing (OFDM) is getting popular for high bandwidth digital communication. Since its sub-carrier spacing is small, OFDM performance is easily degraded by Doppler Frequency Error. This paper proposes a Frequency Domain Radio frequency shift canceller. Simulation result shows roughly two times higher Doppler shift performance was obtained for 64QAM, 8K-FFT OFDM system. |
| Title | A New Architecture Extension for Mitigation of Permanent Functional Unit Faults Using Hot-Swapping Concepts |
| Author | *Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroyuki Ochi (Kyoto University, Japan), Yukihiro Nakamura (Ritsumeikan University, Japan) |
| Page | pp. 177 - 182 |
| Keyword | Hot-Swapping, Dynamically Re-configurable, Fault-tolerant, Dependable Computing, Coarse-grained ALU array |
| Abstract | In this paper, we propose a new architecture extension suitable for arrays of functional units, that will provide testing and replacement of faulty units, without interrupting normal system operation. The extension relies on data-path switching controlled by a hot-swapping algorithm, by use of which functional units are tested and replaced by spares if necessary, ensuring permanent operation while the spares last. A case study is presented on a sample architecture. The Hot-Swapping functionality could be added with an overhead of 74-87% based on the granularity of the native array. |
| Title | A Bottom-Up Exploration Approach for 3D Graphics Hardware Accelerator in Consumer Electronics |
| Author | *Chi-Tsai Yeh, Liang-Bi Chen, Ching-Yuan Lin, Hung-Yu Chen, Ing-Jer Huang (Department of Computer Science and Engineering, National Sun Yat-Sen University, Taiwan) |
| Page | pp. 183 - 188 |
| Keyword | 3D Graphics, SystemC, SoC, System-Level, ESL |
| Abstract | 3D Graphics (3DG) application is generally used in consumer electronics which is an inevitable tendency in the future. Usually, we use high abstraction-level to model a complex system like 3DG SoC. However, the concerned issue is that how to use an efficient method to achieve the required performance within the cost constraint. We propose a bottom-up exploration approach by using SystemC that progressively improve system performance. According to result, we improve 198% at geometry function and 69% at rendering function, respectively, altogether. |
| Title | Small Area Multipliers Utilizing the Sum of Operands |
| Author | *Hirotaka Kawashima, Naofumi Takagi (Nagoya University, Japan) |
| Page | pp. 189 - 194 |
| Keyword | VLSI, arithmetic circuit, multiplication |
| Abstract | A method to halve the number of partial product bits in multiplication is proposed. An integrated partial product (IPP) is introduced. The proposed method separates the IPP into four cases according to a pair of a multiplicand bit and a multiplier bit. The value of the IPP is obtained by selecting a value from the four cases. The total number of IPP bits becomes half the total number of ordinary partial product bits by utilizing the sum of the operands. The proposed method is applicable to both unsigned and signed multiplication. Multipliers using the proposed method are smaller than array multipliers and Wallace multipliers by approximately 30%, and smaller than multipliers with radix-4 Booth's method by approximately 10%. |