| Title | A Design Optimization of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique |
| Author | *Shoichi Hara, Rui Murakami, Kenichi Okada, Akira Matsuzawa (Tokyo Institute of Technology, Japan) |
| Page | pp. 399 - 404 |
| Keyword | VCO, phase-noise, multiple-divide, ILFD |
| Abstract | The multiple-divide technique, using the multi-ratio frequency divider, has a possibility to improve FoM of VCO. This paper proposes a design optimization of LC-VCO using the multiple-divide technique. In the simulated results using 90-nm CMOS model parameters, the optimum frequency range, achieving better than -187.0 dBc/Hz of FoM, can be extended from 6.5 - 12.5GHz to 1.5 - 12.5 GHz. The proposed multiple-divide technique can provide a lower phase-noise, lower power consumption, smaller layout area of LC-VCO. |
| Title | Numerical Flicker Noise Model for Dual Channel FETs |
| Author | *Chia-Yu Chen, Yang Liu, Robert W. Dutton (Stanford University, United States), Junko Sato-Iwanaga, Akira Inoue, Haruyuki Sorada (Matsushita Electric Industrial Co.,Ltd., Japan) |
| Page | pp. 405 - 409 |
| Keyword | Flicker noise, heterostructure, MOSFETs, SiGe, TCAD |
| Abstract | A layer-dependent flicker noise model is proposed to predict low-frequency noise behavior in dual channel MOSFETs. A numerical noise model is implemented to account for unified number-mobility fluctuations in the buried and parasitic surface channels. A layer-dependent Hooge mobility fluctuation is also included in the numerical model. Based on the advanced TCAD capability the contributions of different flicker noise mechanisms can be quantified and the dominant flicker noise sources in different bias conditions can be discussed. |
| Title | Efficient State Space Enumeration for the Verification of Analog Designs |
| Author | *Pao-Jen Huang, Wei-Hsiang Cheng, Chien-Nan Liu (National Central University, Taiwan) |
| Page | pp. 410 - 415 |
| Keyword | Formal Verification, State Emulation, Analog Verification |
| Abstract | In previous approaches toward analog formal verification, the continuous state space of an analog circuit should be bounded and transformed to a FSM-like discrete model before applying formal methods. It implies that the reachable state space enumeration is the first key step in analog formal verification. In this paper, we propose an efficient state space enumeration approach that treats each MOS transistor as a storage element with 3 states and constructs all possible state combinations of an analog circuit. Because the range concept is considered, the states with similar behavior can be merged to reduce the number of possible states. We also propose an algorithm to analyze the netlist connection and further eliminate unreachable state combinations. Besides the reduction of verification complexity, the proposed method can also help designers to verify the operation range of the circuit without simulation. As shown in the experimental results, the state transition predicted by our approach does match the real circuit behavior very well, which provides another fast solution for the verification of analog designs. |
| Title | A Study on Mobility Degradation Effect for High PSRR Linear Voltage-to-Current Converter Design |
| Author | Chun Wei Lin, *Sheng Feng Lin, You Cheng Huang (National Yunlin University of Science and Technology, Taiwan) |
| Page | pp. 416 - 421 |
| Keyword | voltage-to-current converter, mobility degradation, transconductance, PSRR |
| Abstract | In this work, we propose a linear voltage-to-current converter (VIC) with mobility degradation compensation. Through utilizing the sum of two current sources which operated in linear and saturation region respectively, the nonlinearity of complementary parabolic voltage to current characteristics caused by mobility degradation are minimized. All theoretical analysis and design flow are developed well and a practical chip was fabricated by TSMC 0.35um 3.3V CMOS process with its measured transconductance and current variation are 0.923~1.064 and 1.5% respectively. The experiment results show that the proposed design significantly improves PSRR and the nonlinearity effect of VIC originated from mobility degradation. |
| Title | A Predictive Test Strategy for LNAs for RF CMOS Receivers |
| Author | *Kay Suenaga, Rodrigo Picos, Sebastia Bota, Miquel Roca, Eugeni Isern, Eugeni Garcia-Moreno (University of Balearic Islands, Spain) |
| Page | pp. 422 - 427 |
| Keyword | BiST, LNA, Predictive test, RF test |
| Abstract | In this paper, a Predictive Test strategy is proposed to estimate basic LNA performance parameters (such as S-parameters and IP1dB). This strategy uses easily measurable test observables. The method is suitable to be used in amplifiers embedded in RF receivers. This study presents a full On-Chip test setup, including the circuitry used to generate the input test stimuli needed to obtain the test observables: it consists of an IF generator and an auxiliary mixer. The test area overhead has been kept low by reusing some receiver blocks as test circuitry. RMS estimation errors for the predicted values of S12, S21, S22 and IP1dB are less than 1 %. |
| Title | A Compact On-Chip Testing Scheme for Analog-Mixed Signal Systems Using Two-Step AC and DC Fault Signature Characterizations |
| Author | *Wimol San-Um, Masayoshi Tachibana (Kochi University of Technology, Japan) |
| Page | pp. 428 - 433 |
| Keyword | Analog Testing, BIST, Amplifer |
| Abstract | This paper presents a compact on-chip testing scheme for detecting catastrophic faults in the pre-screening process of defective analog circuits in mixed-signal systems. The technique is based on AC and DC fault signature characterizations, which detect faults by monitoring and analyzing the fault signatures though amplitude and offset of voltage signals. This technique simplifies the design of fault-sensing circuits and provides digital logic test outputs and is applicable in most types of analog circuits. Demonstrations of a two-stage differential amplifier using 0.18-ìm CMOS technology show that fault coverage and area overhead are 97.5% and 15%, respectively. |
| Title | An Assertion-Based Verification Methodology for SystemC-AMS Designs |
| Author | *Stefan Lämmermann (Universität Tübingen, Germany), Alexander Jesser (Universität Frankfurt, Germany), Roland Weiss, Juergen Ruf, Thomas Kropf (Universität Tübingen, Germany), Lars Hedrich (Universität Frankfurt, Germany), Wolfgang Rosenstiel (Universität Tübingen, Germany) |
| Page | pp. 434 - 439 |
| Keyword | Assertion based verification, Mixed-signal verification, Simulation, Heterogeneous System Verification |
| Abstract | Heterogeneous system languages lack on functional and formal verification methodologies. However, there exists a verification gap between the different domains. An assertion-based design method is essential to bridge the verification gap. This requires mixed-signal assertions which include properties from all domains together. Therefore, we extend the formal semantics for mixed-signal assertions with new constraints of analog and transaction level modeling. Our approach improves the assertion-based verification technique with our implemented simulation based checker. The proposed method is a new assertion-based verification methodology for heterogenous systems. The effectiveness is demonstrated on two examples. |
| Title | Reliability Aware Power Grid Optimization with Consideration of Thermal Effects |
| Author | *Haruo Miki, Yoshiyuki Kawakami (Ritsumeikan University, Japan), Masaya Yoshikawa (Meijo University, Japan), Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 440 - 445 |
| Keyword | power grid optimization, thermal analysis, electromigration |
| Abstract | Reliability becomes one of the most important issues for designing LSIfs. Major metrics related to reliability are timing violation risk by IR drop and wire cutoff risk by electric migration. These risks are sensitive to thermal conditions. This paper proposes a new power grid optimization algorithm that considers these thermal effects to get more reliable results. Risks of timing violation and wire cutoff are simultaneously considered and worse risk is minimized by this method. Experimental results depict that our new approach deals with reliability issues with more reality. |
| Title | Analysis of Process Variations in 90-nm CMOS Technology using Ring Oscillators |
| Author | Akihiro Kaya, Koh Johguchi, Shinya Izumi, Hans Jürgen Mattausch, *Tetsushi Koide (Hiroshima University, Japan) |
| Page | pp. 446 - 449 |
| Keyword | Ring oscillator, Process variation, within-wafer, within-die, HiSIM |
| Abstract | Process variations are rapidly increasing as the transistor size is scaled down. Thus, it is necessary to estimate accurately within-die and inter-die variations, in order to construct a design method for correct operation of circuits and integrated systems under these unavoidable variations. Here we report an analysis of ring oscillators, designed in a 90-nm CMOS technology, and the determination of their frequency variations for different stage numbers and supply voltages. The measurement results are also used to separate the within-wafer and within-die variations. In particular, the variation dependence on the supply voltages shows that within-die variations increase 3-times faster than the within-wafer variations when the power-supply voltage is reduced from 1.0 V to 0.6 V. Consequently, the within-die variations are expected to limit the low-power operation of VLSI circuits in future small scale process technologies. |
| Title | Yield Improvement in Memory Compiler Generated SRAM with Inter-Die Variations |
| Author | Chia-Chi Hsiao, *Hung-Ming Chen (National Chiao Tung University, Taiwan), Ching-Che Chung (National Chung Cheng University, Taiwan) |
| Page | pp. 450 - 455 |
| Keyword | Yield Improvement, SRAM, Process Variations |
| Abstract | As the technology scales down to nanometer, the yield degradation caused by inter-die variations is getting worse. Using adaptive body bias is an effective method to eliminate the yield degradation, however we need to know a die having high threshold voltage or low threshold voltage (also called process corner) in order to use this technique. Unfortunately, it is hard to detect the process corner when PMOS and NMOS variations are uncorrelated. In this paper, we propose some improved circuits of delay monitor and leakage monitor for both PMOS and NMOS, which are uncorrelated in inter-die variations. The experimental results show that our circuits can clearly distinguish each process corner of PMOS and NMOS, thus improve the yield obviously by adopting correct body bias. |
| Title | Asynchronous Differential Capacitance-to-Digital Converter for Capacitive Sensors |
| Author | *Tuan Minh Vo, Yasuhide Kuramochi, Masaya Miyahara, Takashi Kurashina, Akira Matsuzawa (Tokyo Institute of Technology, Japan) |
| Page | pp. 456 - 461 |
| Keyword | DIFFERENTIAL, ASYNCHRONOUS, CAPACITANCE-TO-DIGITAL CONVERTER, LOW-POWER |
| Abstract | This paper proposed a 10-bit low-power asynchronous differential capacitance-to-digital converter (CDC) for capacitive sensors. The proposed differential architecture makes the circuit insensitive to variations of sensor capacitance. Additionally, asynchronous mechanism and a dynamic regenerative comparator are utilized to lower the overall power of the circuit. Simulation results show that the effective number of bits (ENOB) of the proposed circuit is improved by 3.3 bits at Nyquist frequency as compared with previous work. The power consumption at 262 kHz is 8.45uA, which reducing from the previous work by 95% at the same frequency. |
| Title | New Device-Level Technology Retargeting Algorithm with Fixed-Topology Constraints |
| Author | *Ying-Zhih Chuang, De-Shiun Fu, Yih-Lang Li (Computer Science Department National Chiao Tung University, Taiwan) |
| Page | pp. 462 - 467 |
| Keyword | Migration, Constraint Graph, Topology |
| Abstract | Traditional constraint graph approaches only consider space utilization and therefore generate a compact cell layout with most a majority of the change in the shape and topology of interconnection. Moreover, traditional constraint-graph based migration algorithms have no capability to handle 45 degree wires. In this study, we propose and enhanced edge-based constraint graph compaction algorithm to prevent the distortion of the original shape and topology for digital devices. Based on the edge-based algorithm, a pseudo 45 degree edge model is integrated into our device migration framework. This model strengthens our device migration framework to process 45 degree wires. Furthermore, an effective wire extraction algorithm is proposed to identify interconnection between devices. The experimental results show that the proposed device migration algorithm can fast yield compact layout that conforms to new design rules without layout distortion. |
| Title | A Design of Active Decoupling Circuit for the Substrate Noise Reduction on a Mixed Signal LSI |
| Author | *Daisuke Satoh, Nobuhiko Nakano (Keio University, Japan) |
| Page | pp. 468 - 472 |
| Keyword | substrate noise, active decoupling, mixed signal, substrate compact model |
| Abstract | This paper presents an active decoupling circuit chip design with a variable substrate contact array to change the impedance to substrate. To simulate the substrate noise propagation, we made a substrate compact model using 3D field solver. The simulation results show the active decoupling can damp substrate noise to about 16-45 % in certain cases. The active decoupling circuit designed in this work was better performance under a few MHz than previously designed. |
| Title | A Multiphase Digital Controlled Oscillator with DVC Technique |
| Author | *Pao-Lung Chen, Chun-Fu Liu, Tsung-Hsiang Lin (National Kaohsiung First University of Science and Technology, Taiwan) |
| Page | pp. 473 - 476 |
| Keyword | DCO, ADPLL, VCO |
| Abstract | This paper presents a multiphase digital controlled oscillator with digital to voltage converter (DVC) technique. This multiphase digital controlled oscillator works from 102 MHz to 735 MHz with six coarse controlled bits and seven fine controlled bits. The power consumption of the ten phases output is 17mW at 735 MHz based on post-layout simulation in TSMC 0.18 um 1P6M CMOS process. The core area is 133 um x 117u m. |
| Title | A Wireless Chip for Intra-Oral Temperature Measurement |
| Author | *Tomohiro Ishikawa, Yoshihiro Masui, Koh Johguchi, Takeshi Yoshida, Yuji Murakami (Hiroshima University, Japan) |
| Page | pp. 477 - 481 |
| Keyword | Wireless, Temperature, Measurement, Intra-Oral, Denture |
| Abstract | A CMOS chip for an intra-oral temperature measurement is designed. The chip measures temperature with relatively slow sampling rate (<10Hz), converts it into serial data and sends them wirelessly. The measurement can provide a good benchmark of swallowing function. The chip is molded into a polymer based denture with a button battery and a crystal oscillator. To maintain acceptable feel of wear, there is a constraint on size, and as a result, there is strong demand for low power consumption. Each circuit block such as sensor, pre-amplifier, analog-to-digital converter (ADC) and static random access memory (SRAM) are designed in custom and evaluated by SPICE simulation. |