The 15th Workshop on Synthesis And System Integration of Mixed Information technologies
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Monday, March 9, 2009


Opening (Waikele) 9:00 - 9:15
I1 (Waikele) Invited Talk I 9:15 - 10:00
R1 (Waikele & Kaneohe) Poster I: Low Power and Timing 10:00 - 11:45
Lunch Break 11:45 - 13:15
K1 (Manza) Keynote Speech I 13:15 - 14:15
R2 (Manza & Kaneohe) Poster II: System Algorithm and Design 14:15 - 16:00
I2 (Manza) Invited Talk II 16:00 - 16:45
R3 (Manza & Kaneohe) Poster III: High Performance and Special Feature Design 16:45 - 18:30
Banquet (Manza) 19:00 - 21:00

Tuesday, March 10, 2009


I3 (Manza) Invited Talk III 9:00 - 9:45
R4 (Manza & Kaneohe) Poster IV: Physical Design and Methodology 9:45 - 11:30
Lunch Break 11:30 - 13:00
K2 (Manza) Keynote Speech II 13:00 - 14:00
R5 (Manza & Kaneohe) Poster V: Mixed Signal Design 14:00 - 15:45
D (Manza) Panel Discussion 15:45 - 17:15
Closing (Manza) 17:15 - 17:25

List of Papers

Remark: The presenter of each paper is marked with "*".

Monday, March 9, 2009

Invited Talk I
Time: 9:15 - 10:00 Monday, March 9, 2009
Location: Waikele
Chair: Kimiyoshi Usami (Shibaura Inst. of Tech., Japan)

I1-1 (Time: 9:15 - 10:00)

Title	Analysis and Optimization of Power-Gated Designs
Author	Ming-Chao Lee, De-Shiuan Chiou, *Shih-Chieh Chang (National Tsing Hua Univ., Taiwan)
Page	pp. 3 - 8
Detailed information (abstract, keywords, etc)

Poster I: Low Power and Timing
Time: 10:00 - 11:45 Monday, March 9, 2009
Location: Waikele & Kaneohe
Chairs: Jimmy Chien-Nan Liu (National Central Univ., Taiwan), Hiroaki Yoshida (Univ. of Tokyo, Japan)

R1-1 (Time: 10:00 - 10:03)

Title	A New RTL Power Macro-modeling and Efficient Power Estimation Scheme
Author	*Masaaki Ohtsuki, Masato Kawai, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 11 - 16
Detailed information (abstract, keywords, etc)

R1-2 (Time: 10:03 - 10:06)

Title	An Efficient Hardware Circuit Simulator for Power Grid Optimization System
Author	*Taiki Hashizume, Shinichi Nishizawa, Hisako Sugano (Ritsumeikan Univ., Japan), Masaya Yoshikawa (Meijo Univ., Japan), Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 17 - 22
Detailed information (abstract, keywords, etc)

R1-3 (Time: 10:06 - 10:09)

Title	IR-Drop-Aware Buffer/Flip-Flop Station Planning in Floorplan Design
Author	Hsin-Hwa Pan (AnaGlobe Technology, Inc., Taiwan), *Hung-Ming Chen (National Chiao Tung Univ., Taiwan), Chia-Yi Chang (Realtek Semiconductor Corp., Taiwan)
Page	pp. 23 - 28
Detailed information (abstract, keywords, etc)

R1-4 (Time: 10:09 - 10:12)

Title	IR Drop-Driven Algorithm for Standard Cell Placement Considering Timing Windows
Author	*Naoki Kitamura, Nobuyuki Umakoshi, Kaoru Okazaki (Osaka Electro-Communication Univ., Japan), Masayuki Terai (Osaka Gakuin Univ., Japan)
Page	pp. 29 - 34
Detailed information (abstract, keywords, etc)

R1-5 (Time: 10:12 - 10:15)

Title	Energy Dissipation Reduction of Arithmetic Operations with Valid Digits
Author	*Kazuhito Ito, Yorito Nagasaka (Saitama Univ., Japan)
Page	pp. 35 - 40
Detailed information (abstract, keywords, etc)

R1-6 (Time: 10:15 - 10:18)

Title	Power Efficiency Index for Low Power LSI Design
Author	*Yutaka Tamiya (Fujitsu Laboratories Ltd., Japan), Masahiro Fujita (Univ. of Tokyo, Japan)
Page	pp. 41 - 46
Detailed information (abstract, keywords, etc)

R1-7 (Time: 10:18 - 10:21)

Title	A Microprocessor-based Architecture for a Smart in vivo Biosensor
Author	*Yohei Fukumizu, Tomonori Izumi, Hironori Yamauchi (Ritsumeikan Univ., Japan)
Page	pp. 47 - 51
Detailed information (abstract, keywords, etc)

R1-8 (Time: 10:21 - 10:24)

Title	Low Power Unequal Error Protection Media System Based on Error Concealment in H.264/AVC
Author	*Yichun Tang, Jun Wang, Naoki Tajima, Satoshi Goto (Waseda Univ., Japan)
Page	pp. 52 - 57
Detailed information (abstract, keywords, etc)

R1-9 (Time: 10:24 - 10:27)

Title	An Experimental Comparison of Power Analysis Attacks against RSA Processors on ASIC and FPGA
Author	*Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki (Tohoku Univ., Japan), Akashi Satoh (AIST, Japan)
Page	pp. 58 - 63
Detailed information (abstract, keywords, etc)

R1-10 (Time: 10:27 - 10:30)

Title	On Using Spare Cells for Functional Changes with Wirelength Consideration
Author	*Yun-Ru Wu, Shu-Yun Chen (Realtek Semiconductor Crop., Taiwan), Kuang-Yao Lee, Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 64 - 69
Detailed information (abstract, keywords, etc)

R1-11 (Time: 10:30 - 10:33)

Title	A Gaussian Mixture Model to Propagate Delay and Slew Distributions Together in Statistical Timing Analysis
Author	*Shingo Takahashi, Shuji Tsukiyama (Chuo Univ., Japan)
Page	pp. 70 - 75
Detailed information (abstract, keywords, etc)

R1-12 (Time: 10:33 - 10:36)

Title	Embedded Delay Detectors to Choose the Fastest Route in FPGAs for Variation-aware Reconfiguration
Author	*Yohei Kume, Yuuri Sugihara, Camlai Ngo, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 76 - 81
Detailed information (abstract, keywords, etc)

R1-13 (Time: 10:36 - 10:39)

Title	Performance-Driven Architectural Synthesis for Multicycle Communication
Author	*Chia-I Chen, Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Page	pp. 82 - 87
Detailed information (abstract, keywords, etc)

R1-14 (Time: 10:39 - 10:42)

Title	A Fast Regular Expression Matching Engine for an FPGA-based Network Intrusion Detection System
Author	*Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ., Japan)
Page	pp. 88 - 93
Detailed information (abstract, keywords, etc)

R1-15 (Time: 10:42 - 10:45)

Title	Fast Division Circuit in GF(2^m) Based on the Extended Euclid's Algorithm with Parallelization of Modular Reductions
Author	*Katsuki Kobayashi, Naofumi Takagi (Nagoya Univ., Japan)
Page	pp. 94 - 99
Detailed information (abstract, keywords, etc)

Keynote Speech I
Time: 13:15 - 14:15 Monday, March 9, 2009
Location: Manza
Chair: Masahiro Fukui (Ritsumeikan Univ., Japan)

K1-1 (Time: 13:15 - 14:15)

Title	Future Direction of Integrated Nano and Micro-systems
Author	Cyril Condemine, Marc Belleville, *Ahmed Jerraya (CEA-LETI, France)
Page	pp. 103 - 104
Detailed information (abstract, keywords, etc)

Poster II: System Algorithm and Design
Time: 14:15 - 16:00 Monday, March 9, 2009
Location: Manza & Kaneohe
Chairs: Juinn-Dar Huang (National Chiao Tung Univ., Taiwan), Kazuhito Ito (Saitama Univ., Japan)

R2-1 (Time: 14:15 - 14:18)

Title	Static Scheduling of Dynamic Execution for High-Level Synthesis
Author	*Yuki Toda, Nagisa Ishiura, Kousuke Sone (Kwansei Gakuin Univ., Japan)
Page	pp. 107 - 112
Detailed information (abstract, keywords, etc)

R2-2 (Time: 14:18 - 14:21)

Title	TRANSYSCTOR: A General Methodology and Framework for Rule-Based Transformation and Refactoring of SystemC Designs
Author	*Alexander Viehl, Jordan Dukadinov, Oliver Bringmann (FZI Forschungszentrum Informatik, Germany), Wolfgang Rosenstiel (Univ. of Tübingen, Germany)
Page	pp. 113 - 118
Detailed information (abstract, keywords, etc)

R2-3 (Time: 14:21 - 14:24)

Title	An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits
Author	*Kosuke Shioki, Narumi Okada, Toshiro Ishihara, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 119 - 124
Detailed information (abstract, keywords, etc)

R2-4 (Time: 14:24 - 14:27)

Title	An Efficient Exploring Method of Room-to-Room Floorplan
Author	*Yosuke Takahashi, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan)
Page	pp. 125 - 130
Detailed information (abstract, keywords, etc)

R2-5 (Time: 14:27 - 14:30)

Title	A Conjecture on the Number of Extra Registers in Safe Clocking-Based Register Assignment
Author	*Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST, Japan)
Page	pp. 131 - 136
Detailed information (abstract, keywords, etc)

R2-6 (Time: 14:30 - 14:33)

Title	Circuit Acyclic Clustering with Input/Output Constraints and Applications
Author	*Rung-Bin Lin, Tsung-Han Lin, Shin-An Wu (Yuan Ze Univ., Taiwan)
Page	pp. 137 - 142
Detailed information (abstract, keywords, etc)

R2-7 (Time: 14:33 - 14:36)

Title	On the Number of Rooms in a Rectangular Solid Dissection
Author	*Hidenori Ohta (Tokyo Univ. of Agri. and Tech., Japan), Toshinori Yamada (Saitama Univ., Japan), Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan)
Page	pp. 143 - 148
Detailed information (abstract, keywords, etc)

R2-8 (Time: 14:36 - 14:39)

Title	Assertion Checker Synthesis for FPGA Emulation
Author	*Chengjie Zang, Qixin Wei, Shinji Kimura (Waseda Univ., Japan)
Page	pp. 149 - 154
Detailed information (abstract, keywords, etc)

R2-9 (Time: 14:39 - 14:42)

Title	Automatic Pipeline Generation for FPGA-based Prototyping
Author	*Weijie Xing, Kai Zheng (Waseda Univ., Japan), Tomoo Kimura, Shunichi Kuromaru, Kouji Kai (Panasonic Corp., Japan), Shinji Kimura (Waseda Univ., Japan)
Page	pp. 155 - 160
Detailed information (abstract, keywords, etc)

R2-10 (Time: 14:42 - 14:45)

Title	VLSI Design of a Handwritten-Character Learning and Recognition system based on Associative Memory
Author	*Shogo Sakakibara, Wataru Imafuku, Akio Kawabata, Tania Ansari, Hans Jürgen Mattausch, Tetsushi Koide (Hiroshima Univ., Japan)
Page	pp. 161 - 166
Detailed information (abstract, keywords, etc)

R2-11 (Time: 14:45 - 14:48)

Title	Improved Region-Growing Image-Segmentation Algorithm Based on the HSV Color Space
Author	*Tatsuya Sugahara, Keita Okazaki, Naomi Nagaoka, Ryosuke Kimura, Tetsushi Koide, Hans Jürgen Mattausch (Hiroshima Univ., Japan)
Page	pp. 167 - 171
Detailed information (abstract, keywords, etc)

R2-12 (Time: 14:48 - 14:51)

Title	The Design of Frequency Domain Inter Carrier Interference (ICI) Canceling Circuit caused by Radio Frequency Shift for OFDM Receiver
Author	*Kenta Nohara, Tomohisa Wada (Univ. of the Ryukyus, Japan)
Page	pp. 172 - 176
Detailed information (abstract, keywords, etc)

R2-13 (Time: 14:51 - 14:54)

Title	A New Architecture Extension for Mitigation of Permanent Functional Unit Faults Using Hot-Swapping Concepts
Author	*Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroyuki Ochi (Kyoto Univ., Japan), Yukihiro Nakamura (Ritsumeikan Univ., Japan)
Page	pp. 177 - 182
Detailed information (abstract, keywords, etc)

R2-14 (Time: 14:54 - 14:57)

Title	A Bottom-Up Exploration Approach for 3D Graphics Hardware Accelerator in Consumer Electronics
Author	*Chi-Tsai Yeh, Liang-Bi Chen, Ching-Yuan Lin, Hung-Yu Chen, Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)
Page	pp. 183 - 188
Detailed information (abstract, keywords, etc)

R2-15 (Time: 14:57 - 15:00)

Title	Small Area Multipliers Utilizing the Sum of Operands
Author	*Hirotaka Kawashima, Naofumi Takagi (Nagoya Univ., Japan)
Page	pp. 189 - 194
Detailed information (abstract, keywords, etc)

Invited Talk II
Time: 16:00 - 16:45 Monday, March 9, 2009
Location: Manza
Chair: Takao Onoye (Osaka Univ., Japan)

I2-1 (Time: 16:00 - 16:45)

Title	Design Challenges and Technologies for Cell Broadband Engine
Author	*Yoshio Masubuchi (Toshiba Corp., Japan)
Page	p. 197
Detailed information (abstract, keywords, etc)

Poster III: High Performance and Special Feature Design
Time: 16:45 - 18:30 Monday, March 9, 2009
Location: Manza & Kaneohe
Chairs: Nobuyuki Nishiguchi (STARC, Japan), Hiroyuki Higuchi (Fujitsu Microelectronics Ltd., Japan)

R3-1 (Time: 16:45 - 16:48)

Title	Evaluation of the Performance of the MIMD Mode of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application
Author	*Shohei Nomoto, Shorin Kyo, Shinichiro Okazaki (NEC, Japan)
Page	pp. 201 - 206
Detailed information (abstract, keywords, etc)

R3-2 (Time: 16:48 - 16:51)

Title	Pipelining SHA-2 Implementations using Carry Save Adders
Author	*Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi (Ritsumeikan Univ., Japan)
Page	pp. 207 - 212
Detailed information (abstract, keywords, etc)

R3-3 (Time: 16:51 - 16:54)

Title	Hardware Accelerator for Feature Point Detection Part of SIFT Algorithm & Corresponding Hardware-Friendly Modification
Author	*Jingbang Qiu, Tianci Huang, Takeshi Ikenaga (Waseda Univ., Japan)
Page	pp. 213 - 218
Detailed information (abstract, keywords, etc)

R3-4 (Time: 16:54 - 16:57)

Title	Variability Characterization and Tolerance on Throughput and Power for Chip-Multiprocessors
Author	*Wan-Yu Lee, Iris Hui-Ru Jiang (National Chiao Tung Univ., Taiwan)
Page	pp. 219 - 223
Detailed information (abstract, keywords, etc)

R3-5 (Time: 16:57 - 17:00)

Title	A Ternary Multi-Ported Content Addressable Memory Architecture utilizing Asynchronous Multiple Search-Operation Technology
Author	*Takeshi Kumaki, Masaharu Tagami, Yuta Imai, Tetsushi Koide, Hans Jürgen Mattausch (Hiroshima Univ., Japan)
Page	pp. 224 - 229
Detailed information (abstract, keywords, etc)

R3-6 (Time: 17:00 - 17:03)

Title	A Hardware Design for the First Pass of A Large Vocabulary Continuous Speech Recognition System
Author	*Akihiko Eguchi, Joe Hashimoto (Kinki Univ., Japan), Makoto Saituji (NEC Electronics, Japan), Akihisa Yamada (Sharp Corp., Japan), Takashi Kambe (Kinki Univ., Japan)
Page	pp. 230 - 235
Detailed information (abstract, keywords, etc)

R3-7 (Time: 17:03 - 17:06)

Title	Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability
Author	*Younghun Ko, Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye (Osaka Univ., Japan)
Page	pp. 236 - 241
Detailed information (abstract, keywords, etc)

R3-8 (Time: 17:06 - 17:09)

Title	Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm
Author	*Ming-Chih Chen (National Kaohsiung First Univ. of Science and Tech., Taiwan), Shen-Fu Hsiao (National Sun Yat-Sen Univ., Taiwan)
Page	pp. 242 - 247
Detailed information (abstract, keywords, etc)

R3-9 (Time: 17:09 - 17:12)

Title	DSP Array Breadboard System for Application on Foreground Segmentation
Author	*Bin Wu, Takao Nishitani (Tokyo Metropolitan Univ., Japan)
Page	pp. 248 - 253
Detailed information (abstract, keywords, etc)

R3-10 (Time: 17:12 - 17:15)

Title	An Interface for Representing Dynamically Reconfigurable Architectures by using Graph with Configuration Information
Author	*Vasutan Tunbunheng, Hideharu Amano (Keio Univ., Japan)
Page	pp. 254 - 259
Detailed information (abstract, keywords, etc)

R3-11 (Time: 17:15 - 17:18)

Title	A Case Study of Clockless Bundled-data On-chip Interconnect Design using Double Edge Triggered Flip-flops
Author	*Katsunori Tanaka, Yuichi Nakamura (NEC Corp., Japan)
Page	pp. 260 - 265
Detailed information (abstract, keywords, etc)

R3-12 (Time: 17:18 - 17:21)

Title	A VLSI Architecture of Tone Classification Function-Based Isolated-Word Speech Recognition
Author	*Jirabhorn Chaiwongsai, Werapon Chiracharit, Kosin Chamnongthai (King Mongkut's Univ. of Tech. Thonburi, Thailand), Yoshikazu Miyanaga (Hokkaido Univ., Japan), Kouji Higuchi (Univ. of Electro-Communications, Japan)
Page	pp. 266 - 270
Detailed information (abstract, keywords, etc)

R3-13 (Time: 17:21 - 17:24)

Title	Speculative Configuration Prefetching for Multi-Context Architectures
Author	*Sven Eisenhardt, Julio Oliveira, Tommy Kuhn, Wolfgang Rosenstiel (Univ. Tübingen, Germany)
Page	pp. 271 - 276
Detailed information (abstract, keywords, etc)

R3-14 (Time: 17:24 - 17:27)

Title	Efficient Mode Selection Algorithm for Inter-Layer Residual Prediction of H.264/SVC
Author	*Yoshitaka Morigami, Shinpei Matsuoka, Tian Song, Takashi Shimamoto (Tokushima Univ., Japan)
Page	pp. 277 - 282
Detailed information (abstract, keywords, etc)

R3-15 (Time: 17:27 - 17:30)

Title	A Case Study on AES Encryption System Design with SystemBuilder
Author	*Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ., Japan)
Page	pp. 283 - 288
Detailed information (abstract, keywords, etc)

Tuesday, March 10, 2009

Invited Talk III
Time: 9:00 - 9:45 Tuesday, March 10, 2009
Location: Manza
Chair: Takashi Kambe (Kinki Univ., Japan)

I3-1 (Time: 9:00 - 9:45)

Title	CMP Service: Past, Present, Future
Author	*Bernard Courtois (CMP, France)
Page	pp. 291 - 298
Detailed information (abstract, keywords, etc)

Poster IV: Physical Design and Methodology
Time: 9:45 - 11:30 Tuesday, March 10, 2009
Location: Manza & Kaneohe
Chairs: Hung-Ming Chen (National Chiao Tung Univ., Taiwan), Yasuhiro Takashima (Univ. of Kitakyushu, Japan)

R4-1 (Time: 9:45 - 9:48)

Title	A Two-Layer Global Router for Ball Grid Array Packages
Author	Yung-Chia Lin, *Kuang-Yao Lee, Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 301 - 306
Detailed information (abstract, keywords, etc)

R4-2 (Time: 9:48 - 9:51)

Title	A Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages
Author	*Yoshiaki Kurata, Yoichi Tomioka, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech., Japan)
Page	pp. 307 - 312
Detailed information (abstract, keywords, etc)

R4-3 (Time: 9:51 - 9:54)

Title	Throughput-Driven Hierarchical Partitioning-Based Placement for Regular Distributed Register Architecture
Author	*Ya-Shih Huang, Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Page	pp. 313 - 317
Detailed information (abstract, keywords, etc)

R4-4 (Time: 9:54 - 9:57)

Title	Overlap-aware Analytical Placement Based on Stable-LSE
Author	*Naoto Funatsu, Yasuhiro Takashima (Univ. of Kitakyushu, Japan)
Page	pp. 318 - 323
Detailed information (abstract, keywords, etc)

R4-5 (Time: 9:57 - 10:00)

Title	Yield Improvement in Gridless Detailed Routing with Redundant Via Insertion
Author	*Chih-Ta Lin, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Page	pp. 324 - 329
Detailed information (abstract, keywords, etc)

R4-6 (Time: 10:00 - 10:03)

Title	Interconnect Utilization of the VPEX Via-Programmable Structured ASIC
Author	*Kazuma Kitamura, Syouta Yamada, Masahide Kawarasaki, Yuuichi Kokusyou (Ritsumeikan Univ., Japan), Usman Ahmed, Guy Lemieux (Univ. of British Columbia, Canada), Masaya Yoshikawa (Meijo Univ., Japan), Takeshi Fujino (Ritsumeikan Univ., Japan)
Page	pp. 330 - 334
Detailed information (abstract, keywords, etc)

R4-7 (Time: 10:03 - 10:06)

Title	Slack-Driven Obstacle-Avoiding Rectilinear Steiner Tree Routing
Author	*Yen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Page	pp. 335 - 340
Detailed information (abstract, keywords, etc)

R4-8 (Time: 10:06 - 10:09)

Title	FLEC: A Framework for System-level Debugging Support, Formal Verification and Static Analysis
Author	*Yoshihisa Kojima, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo, Japan)
Page	pp. 341 - 346
Detailed information (abstract, keywords, etc)

R4-9 (Time: 10:09 - 10:12)

Title	Language-Controlled Integrated Debugging Technique
Author	*Noriaki Suzuki, Junji Sakai (NEC Corp., Japan)
Page	pp. 347 - 351
Detailed information (abstract, keywords, etc)

R4-10 (Time: 10:12 - 10:15)

Title	Soft-error Resiliency Evaluation on Delayed Multiple-modular Flip-Flops
Author	*Jun Furuta, Yusuke Moritani, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 352 - 357
Detailed information (abstract, keywords, etc)

R4-11 (Time: 10:15 - 10:18)

Title	Evaluation of Statistical Method of Estimating Coverage Metrics for Functional Verification
Author	Kohei Hosokawa, *Yuichi Nakamura (NEC, Japan)
Page	pp. 358 - 363
Detailed information (abstract, keywords, etc)

R4-12 (Time: 10:18 - 10:21)

Title	A Fast Approximation Method of Maximum Operation in Statistical Static Timing Analysis for Achieving Specified Yield
Author	*Shun Gokita, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech., Japan)
Page	pp. 364 - 369
Detailed information (abstract, keywords, etc)

R4-13 (Time: 10:21 - 10:24)

Title	Dynamic Model of a Parallel Plate Actuator with Pull-in Consideration for CMOS-MEMS Simultaneous Behavior Anticipation
Author	*Yuheon Yi, Hiroyuki Fujita, Hiroshi Toshiyoshi (Univ. of Tokyo, Japan)
Page	pp. 370 - 373
Detailed information (abstract, keywords, etc)

R4-14 (Time: 10:24 - 10:27)

Title	Support System for ASIC Design based on Sysem Block Diagram
Author	*Koichi Mori (Tokyo Metropolitan Univ., Japan), Yuichi Nakamura (NEC, Japan), Takao Nishitani (Tokyo Metropolitan Univ., Japan)
Page	pp. 374 - 379
Detailed information (abstract, keywords, etc)

R4-15 (Time: 10:27 - 10:30)

Title	Equivalence Checking of Loops Before and After Pipelining by Applying Symbolic Simulation and Induction
Author	*Shanghua Gao, Takeshi Matsumoto, Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo, Japan)
Page	pp. 380 - 385
Detailed information (abstract, keywords, etc)

Keynote Speech II
Time: 13:00 - 14:00 Tuesday, March 10, 2009
Location: Manza
Chair: Masahiro Fukui (Ritsumeikan Univ., Japan)

K2-1 (Time: 13:00 - 14:00)

Title	Future Design and Tool Directions for Mixed-signal IC Design in Nanometer CMOS
Author	*Georges Gielen (Katholieke Universiteit Leuven, Belgium)
Page	pp. 389 - 396
Detailed information (abstract, keywords, etc)

Poster V: Mixed Signal Design
Time: 14:00 - 15:45 Tuesday, March 10, 2009
Location: Manza & Kaneohe
Chairs: Ikuo Harada (NTT, Japan), Yutaka Tamiya (Fujitsu Labs., Ltd., Japan)

R5-1 (Time: 14:00 - 14:03)

Title	A Design Optimization of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique
Author	*Shoichi Hara, Rui Murakami, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Page	pp. 399 - 404
Detailed information (abstract, keywords, etc)

R5-2 (Time: 14:03 - 14:06)

Title	Numerical Flicker Noise Model for Dual Channel FETs
Author	*Chia-Yu Chen, Yang Liu, Robert W. Dutton (Stanford Univ., United States), Junko Sato-Iwanaga, Akira Inoue, Haruyuki Sorada (Matsushita Electric Industrial Co.,Ltd., Japan)
Page	pp. 405 - 409
Detailed information (abstract, keywords, etc)

R5-3 (Time: 14:06 - 14:09)

Title	Efficient State Space Enumeration for the Verification of Analog Designs
Author	*Pao-Jen Huang, Wei-Hsiang Cheng, Chien-Nan Liu (National Central Univ., Taiwan)
Page	pp. 410 - 415
Detailed information (abstract, keywords, etc)

R5-4 (Time: 14:09 - 14:12)

Title	A Study on Mobility Degradation Effect for High PSRR Linear Voltage-to-Current Converter Design
Author	Chun Wei Lin, *Sheng Feng Lin, You Cheng Huang (National Yunlin Univ. of Science and Tech., Taiwan)
Page	pp. 416 - 421
Detailed information (abstract, keywords, etc)

R5-5 (Time: 14:12 - 14:15)

Title	A Predictive Test Strategy for LNAs for RF CMOS Receivers
Author	*Kay Suenaga, Rodrigo Picos, Sebastia Bota, Miquel Roca, Eugeni Isern, Eugeni Garcia-Moreno (Univ. of Balearic Islands, Spain)
Page	pp. 422 - 427
Detailed information (abstract, keywords, etc)

R5-6 (Time: 14:15 - 14:18)

Title	A Compact On-Chip Testing Scheme for Analog-Mixed Signal Systems Using Two-Step AC and DC Fault Signature Characterizations
Author	*Wimol San-Um, Masayoshi Tachibana (Kochi Univ. of Tech., Japan)
Page	pp. 428 - 433
Detailed information (abstract, keywords, etc)

R5-7 (Time: 14:18 - 14:21)

Title	An Assertion-Based Verification Methodology for SystemC-AMS Designs
Author	*Stefan Lämmermann (Univ. Tübingen, Germany), Alexander Jesser (Universität Frankfurt, Germany), Roland Weiss, Juergen Ruf, Thomas Kropf (Univ. Tübingen, Germany), Lars Hedrich (Universität Frankfurt, Germany), Wolfgang Rosenstiel (Univ. Tübingen, Germany)
Page	pp. 434 - 439
Detailed information (abstract, keywords, etc)

R5-8 (Time: 14:21 - 14:24)

Title	Reliability Aware Power Grid Optimization with Consideration of Thermal Effects
Author	*Haruo Miki, Yoshiyuki Kawakami (Ritsumeikan Univ., Japan), Masaya Yoshikawa (Meijo Univ., Japan), Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 440 - 445
Detailed information (abstract, keywords, etc)

R5-9 (Time: 14:24 - 14:27)

Title	Analysis of Process Variations in 90-nm CMOS Technology using Ring Oscillators
Author	Akihiro Kaya, Koh Johguchi, Shinya Izumi, Hans Jürgen Mattausch, *Tetsushi Koide (Hiroshima Univ., Japan)
Page	pp. 446 - 449
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R5-10 (Time: 14:27 - 14:30)

Title	Yield Improvement in Memory Compiler Generated SRAM with Inter-Die Variations
Author	Chia-Chi Hsiao, *Hung-Ming Chen (National Chiao Tung Univ., Taiwan), Ching-Che Chung (National Chung Cheng Univ., Taiwan)
Page	pp. 450 - 455
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R5-11 (Time: 14:30 - 14:33)

Title	Asynchronous Differential Capacitance-to-Digital Converter for Capacitive Sensors
Author	*Tuan Minh Vo, Yasuhide Kuramochi, Masaya Miyahara, Takashi Kurashina, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Page	pp. 456 - 461
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R5-12 (Time: 14:33 - 14:36)

Title	New Device-Level Technology Retargeting Algorithm with Fixed-Topology Constraints
Author	*Ying-Zhih Chuang, De-Shiun Fu, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Page	pp. 462 - 467
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R5-13 (Time: 14:36 - 14:39)

Title	A Design of Active Decoupling Circuit for the Substrate Noise Reduction on a Mixed Signal LSI
Author	*Daisuke Satoh, Nobuhiko Nakano (Keio Univ., Japan)
Page	pp. 468 - 472
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R5-14 (Time: 14:39 - 14:42)

Title	A Multiphase Digital Controlled Oscillator with DVC Technique
Author	*Pao-Lung Chen, Chun-Fu Liu, Tsung-Hsiang Lin (National Kaohsiung First Univ. of Science and Tech., Taiwan)
Page	pp. 473 - 476
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R5-15 (Time: 14:42 - 14:45)

Title	A Wireless Chip for Intra-Oral Temperature Measurement
Author	*Tomohiro Ishikawa, Yoshihiro Masui, Koh Johguchi, Takeshi Yoshida, Yuji Murakami (Hiroshima Univ., Japan)
Page	pp. 477 - 481
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Panel Discussion
Time: 15:45 - 17:15 Tuesday, March 10, 2009
Location: Manza
Chair: Atsushi Takahashi (Tokyo Inst. of Tech., Japan)

D-1 (Time: 15:45 - 17:15)

Title	How to Design the Future Mixed Signal LSIs?
Author	Organizer & Moderator: Akira Matsuzawa (Tokyo Inst. of Tech., Japan), Panelists: Georges Gielen (Katholieke Universiteit Leuven, Belgium), Mar Hershenson (Magma Design Automation, Inc., United States), Shoji Kawahito (Shizuoka Univ., Japan), Shiro Dosho (Panasonic Corp., Japan)
Page	p. 485
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The 15th Workshop on Synthesis And System Integration of Mixed Information technologies Technical Program

Session Schedule

List of Papers

The 15th Workshop on Synthesis And System Integration of Mixed Information technologies
Technical Program