| Title | Power-Conscious Synthesis of Parallel Prefix Adders under Bitwise Timing Constraints |
| Author | *Taeko Matsunaga, Shinji Kimura (Waseda Univ., Japan), Yusuke Matsunaga (Kyushu Univ., Japan) |
| Page | pp. 7 - 14 |
| Detailed information (abstract, keywords, etc) | |
| Title | Design of a Combined Circuit for Multiplication and Inversion in GF(2m) |
| Author | *Katsuki Kobayashi, Naofumi Takagi (Nagoya Univ., Japan) |
| Page | pp. 15 - 20 |
| Detailed information (abstract, keywords, etc) | |
| Title | Associative Memory Design Realizing Reference-Pattern Recognition and Learning based on Short/Long-Term Storage Concept |
| Author | *Shogo Sakakibara, Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi , Hans Jüergen Mattausch, Tetsushi Koide (Hiroshima Univ., Japan) |
| Page | pp. 21 - 25 |
| Detailed information (abstract, keywords, etc) | |
| Title | Acceleration of Advanced Encryption Standard (AES) Processing on a CAM Enhanced Super Parallel SIMD Processor |
| Author | *Masaharu Tagami, Masakatsu Ishizaki, Takeshi Kumaki, Yutaka Kono, Tetsushi Koide, Hans Jüergen Mattausch (Hiroshima Univ., Japan), Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas Technology Corp., Japan) |
| Page | pp. 26 - 31 |
| Detailed information (abstract, keywords, etc) | |
| Title | Hardware Realization of Two-Stage Pattern Matching System using Fully-Parallel Associative Memories |
| Author | *Md. Anwarul Abedin, Yuki Tanaka, Shogo Sakakibara, Ali Ahmadi , Tetsushi Koide, Hans Jüergen Mattausch (Hiroshima Univ., Japan) |
| Page | pp. 32 - 37 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Fast Differential-Amplifier-Based Winner-Search circuit for Fully Parallel Associative Memories |
| Author | *Yuki Tanaka, Md. Anwarul Abedin, Shogo Sakakibara, Tetsushi Koide, Hans Jüergen Mattausch (Hiroshima Univ., Japan) |
| Page | pp. 38 - 41 |
| Detailed information (abstract, keywords, etc) | |
| Title | Reducing the Dynamic Energy Consumption in the Multi-Layer Memory of Embedded Multimedia Processing Systems |
| Author | *Ilie I. Luican (Univ. of Illinois, Chicago, United States), Hongwei Zhu (ARM, Inc., United States), Florin Balasa (Southern Utah Univ., United States), Dhiraj K. Pradhan (Univ. of Bristol, Great Britain) |
| Page | pp. 42 - 48 |
| Detailed information (abstract, keywords, etc) | |
| Title | An Output Probability Computation Circuit Design for Real Time Speech Recognition |
| Author | *Joe Hashimoto, Akihiko Eguchi, Makoto Saituji (Kinki Univ., Japan), Akihisa Yamada (Sharp Corp., Japan), Takashi Kambe (Kinki Univ., Japan) |
| Page | pp. 49 - 55 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Hybrid Memory Architecture for Low Power Embedded System Design |
| Author | *Tadayuki Matsumura, Yuriko Ishitobi, Tohru Ishihara, Maziar Goudarzi, Hiroto Yasuura (Kyushu Univ., Japan) |
| Page | pp. 56 - 62 |
| Detailed information (abstract, keywords, etc) | |
| Title | An Accurate and Efficient Lane Recognition Algorithm for Automotive Active Safety System |
| Author | *Yusuke Watanabe, Masahiro Fukui (Ritsumeikan Univ., Japan) |
| Page | pp. 63 - 68 |
| Detailed information (abstract, keywords, etc) | |
| Title | Performance Evaluation of Region-Growing Image Segmentation Using Two-Dimensional Image-Block Scanning |
| Author | *Keita Okazaki, Kazutoshi Awane, Kosuke Yamaoka, Tetsushi Koide, Hans Jüergen Mattausch (Hiroshima Univ., Japan) |
| Page | pp. 69 - 73 |
| Detailed information (abstract, keywords, etc) | |
| Title | An Effective Parallel Coding Architecture Utilizing Characteristics of Multimedia Application |
| Author | *Takeshi Kumaki, Masakatsu Ishizaki, Masaharu Tagami, Tetsushi Koide, Hans Jüergen Mattausch (Hiroshima Univ., Japan) |
| Page | pp. 74 - 80 |
| Detailed information (abstract, keywords, etc) | |
| Title | VLSI Architecture for Real-time Retinex Video Image Enhancement |
| Author | *Kazuyuki Takahashi, Yoshihiro Nozato (Osaka Univ., Japan), Hiroyuki Okuhata (Synthesis Corp., Japan), Takao Onoye (Osaka Univ., Japan) |
| Page | pp. 81 - 86 |
| Detailed information (abstract, keywords, etc) | |
| Title | ΣΔ-Modulator with High Nearby Interferers Suppression by Transmission Zeroes |
| Author | *Takashi Moue, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) |
| Page | pp. 87 - 90 |
| Detailed information (abstract, keywords, etc) | |
| Title | The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time |
| Author | Masaya Miyahara, *Hiroki Endou, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) |
| Page | pp. 91 - 96 |
| Detailed information (abstract, keywords, etc) | |
| Title | A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique |
| Author | *Shuaiqi Wang (Waseda Univ., Japan), Fule Li (Tsinghua Univ., China), Yasuaki Inoue (Waseda Univ., Japan) |
| Page | pp. 97 - 103 |
| Detailed information (abstract, keywords, etc) | |