| Title | Rover: Routing on Via-Configurable Fabrics for Standard-Cell-Like Structured ASICs |
| Author | *Liang-Chi Lai, Hsih-Han Chang, Rung-Bin Lin (Yuan Ze University, Taiwan) |
| Page | pp. 130 - 135 |
| Keyword | structured ASIC, Router, Via-configurable |
| Abstract | In this paper, we present a router called Rover for structured ASICs with via-configurable routing fabrics. We integrate Rover into an industrial design flow. Compared to a commercial yet non-structured ASIC router without a predefined routing fabric, Rover employing a predefined routing fabric on average uses 47% (5%) more wire length (when not counting overhang wire length). It incurs 32% more delay on the longest path, which is much smaller than the 47% increase in wire length. It creates 28.1% overhang wires, which is less than the 35% obtained by previous work. |
| Title | A Physical-Location-Aware Fault Redistribution for Maximum IR-Drop Reduction |
| Author | *Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang (National Tsing Hua University, Taiwan) |
| Page | pp. 136 - 141 |
| Keyword | at-speed testing, IR-drop, X-identification, X-filling |
| Abstract | To guarantee that an application specific integrated circuits (ASIC)meets its timing requirement, at-speed scan testing
becomes an indispensable procedure for verifying the
performance of ASIC. However, at-speed scan test suffers
the test-induced yield loss. Because the switching activity
in test mode is much higher than that in normal mode, the
switching-induced large current drawn causes severe IR drop
and increases gate delay. X-filling is the most commonly
used technique to reduce IR-drop effect during at-speed test.
However, the effectiveness of X-filling depends on the number
and the characteristic of X-bit distribution. In this paper, we
propose a physical-location-aware X-identification which redistributes
faults so that the maximum switching activity is
guaranteed to be reduced after X-filling. The experimental
results on ITC’99 show that our method has an average of
9.55% reduction of maximum switching activity as compared
to a previous work which re-distributes X-bits evenly in all
test vectors. |
| Title | Redundant Via Insertion under Timing Constraints |
| Author | *Chi-Wen Pan, Yu-Min Lee (National Chiao Tung University, Taiwan) |
| Page | pp. 142 - 147 |
| Keyword | redundant via, timing issues, incremental timing analysis |
| Abstract | Redundant via insertion is a useful technique to alleviate the yield loss and elevate the reliability of designed circuit. While extra visa are inserted into the circuit, the electronic properties of circuit will be altered, and the circuit timing will be changed and need to be efficiently re-analyzed. Therefore, a fast timing analyzer is required to assistant the redundant via insertion procedure.
This work develops an efficient redundant via insertion method under timing constraints. Firstly, an effectively incremental circuit timing analysis method is developed, and the redundant via insertion task is transformed into a mixed bipartite-conflict graph matching problem. Then, the insertion problem is solved by a timing-driven minimum weighted matching algorithm.
The experimental results show that the developed algorithm can achieve 3.2% extra insertion rates over the method without considering timing effects in average, and the developed incremental timing analysis mechanism can speed up the runtime of redundant via insertion procedure under timing constraints by over 10 times in average. |
| Title | Optimal Wiring Topology for Electromigration Avoidance |
| Author | Iris Hui-Ru Jiang (National Chiao Tung University, Taiwan), Hua-Yu Chang (National Taiwan University, Taiwan), *Chih-Long Chang (National Chiao Tung University, Taiwan) |
| Page | pp. 148 - 153 |
| Keyword | Reliability, Electromigration, Network flow |
| Abstract | Due to excessive current densities, electromigration
may trigger a permanent open- or short-circuit failure in signal
wires or power networks in analog or mixed-signal circuits. As
the feature size keeps shrinking, this effect becomes a key
reliability concern. Hence, in this paper, we focus on wiring
topology generation for avoiding electromigration at the routing
stage. Prior works tended towards heuristics; on the contrary,
we first claim this problem belongs to class P instead of class
NP-hard. Our breakthrough is, via the proof of the greedychoice
property, we successfully model this problem on a multisource
multi-sink flow network and then solve it by a strongly
polynomial time algorithm. Experimental results prove the
effectiveness and efficiency of our algorithm. |
| Title | Iterative 3D Partitioning for Through-Silicon Via Minimization |
| Author | *Ya-Shih Huang, Yang-Hsiang Liu, Juinn-Dar Huang (National Chiao Tung University, Taiwan) |
| Page | pp. 154 - 159 |
| Keyword | Partitioning, 3D IC, Through-silicon via minimization |
| Abstract | Three-dimensional (3D) integration is a breakthrough technology of growing importance that has the potential to offer significant benefits such as wirelength/power reduction and higher system integration. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a good solution for vertical connection, it also occupies significant silicon estate and incurs reliability problem. Therefore, in this paper, we propose an iterative layer-aware 3D partitioning algorithm, named iLap, for TSV minimization. iLap iteratively applies multi-way min-cut partitioning to gradually divide a given design layer by layer in the bottom-up fashion. Meanwhile, iLap also properly fulfills a special I/O pad constraint incurred by 3D structures to further improve its outcome. The experimental results show that iLap can reduce the number of TSVs by about 35% as compared to several existing methods. |
| Title | 3D-AADI: An Adaptive and Integrable Thermal Simulator According to ADI Concept for 3D IC Physical Design Flow |
| Author | *Sophie Ting-Jung Li, Yu-Min Lee (Department of Electrical Engineering National Chiao Tung University, Taiwan) |
| Page | pp. 166 - 171 |
| Keyword | 3D IC, physical design, thermal simulation, thermal-aware, thermal-driven |
| Abstract | 3D ICs, which deal with cost-e ective achievement by increasing the densities of intercon-nection between dies, are regarded as an attractive alternative solution for overcoming the bottlenecks on 2D planar ICs. In fact, 3D ICs o er the increased system a large number of advantages. However, one of critical challenges is heat dissipation due to higher accumulated power density and lower thermal conductivity of inter-layer dielectrics for vertical stacking layers of active tier. In this way, the management of thermal issues should be considered during physical design stages in spite of only pre-packaging verification on the future highly integrated systems. For these reasons, we develop an adaptive thermal simulator apply our adaptive-3D-thermal-ADI algorithm based on ADI method to provide temperature distribution during 3D IC physical design flow from floor-plan to veri cation.
The simulator constructs adaptive size of simulation grids to avoid the restriction of the most critical position. Furthermore, we apply the concept of ADI iteration method to non-uniform nodes. Eventually, the adaptive-3D-thermal-ADI tool can be regard as both
a reliable thermal simulator and a thermal-driven kernel on 3D IC design flow. The simulator we developed is both adaptive and incremental. |
| Title | An ILP-based Diagnosis Framework For Multiple Open-Segment Defects |
| Author | Chen-Yuan Kao, Chien-Hui Liao, *Charles Hung-Ping Wen (National Chiao Tung University, Taiwan) |
| Page | pp. 172 - 177 |
| Keyword | open defect, Byzantine effect, diagnosis, segment fault |
| Abstract | The faulty responses of an open defect are determined by the Byzantine effect and the physical routing. The Byzantine effect makes such faulty behaviors non-deterministic and depends upon both the pattern and physical information. Therefore, traditional ATPG has difficulty on its fault activation and propagation. This paper proposes a three-stage diagnosis approach of finding combinations of open-segment defects automatically. Path tracing technique helps extract all candidate fault sites from error outputs of failing patterns. An ILP solver enumerates all fault combinations by considering fault candidates and simulation responses. Last, fault simulation identifies true open-segment faults by pruning false cases. Experimental results shows the resolution of the proposed approach is high and only generates an average of <4 combinations for ISCAS85 circuits under the multiple injection of open-segment defects. |
| Title | Dual Supply Voltage Assignment in 3D ICs Considering Thermal Effects |
| Author | *Shu-Han Whi, Yu-Min Lee (National Chiao Tung University, Taiwan) |
| Page | pp. 178 - 183 |
| Keyword | 3D IC, MSV, voltage assignment, voltage island, thermal |
| Abstract | The three dimensional integrated circuits (3D ICs) have been viewed as an effective method to improve chip performance by overcoming the bottleneck of long interconnects in the 2D ICs. However, the higher temperature becomes a serious challenge for 3D ICs and mitigates the advantage of low power. Therefore, it is important to propose an effective method considering thermal effect and power optimization simultaneously.
In this paper, we present a methodology to minimize the total power consumption in the 3D ICs by employing a grid-based dual supply voltage technology. The proposed approach consider three main headings: 1) a voltage assignment process considering three main factor, which consists of sensitivity-based, proximity effect and level shifter budget factor, to be the voltage assignment criterion for power reduction; 2) a 3D electro-thermal simulation to get the temperature of chip; 3) a thermal aware static timing analysis to obtain the thermal related delay of gate in the circuit. The experimental results demonstrate the effectiveness of our voltage assignment method and the thermal effect in circuit performance. |
| Title | Study of Multiple-Output Neuron MOS Current Mirror for Current-Steering Digital-to-Analog Converter |
| Author | *Shuhei Yasumoto, Yuki Nobe, Akio Shimizu, Sumio Fukai (Saga University, Japan), Yohei Ishikawa (Ariake National College of Technology, Japan) |
| Page | pp. 184 - 189 |
| Keyword | digital-to-analog converter, neuron MOSFET, current mirror |
| Abstract | In this paper, we proposed a multiple-output neuron MOS current mirror for a current-steering digital-to-analog (D/A) converter. To improve the output voltage range of current-steering D/A converter, it proposes the current source that operates by the low voltage. It was achieved by using neuron MOS current mirror. HSPICE simulation results show that the proposed circuit is saturation region in Vout > 0.2[V]. Moreover, the proposed circuit is reducing circuit area compared with the conventional circuit. |
| Title | Extended Sequence Pair: A Finite Solution Space for Two-Directional Repeated Placement |
| Author | *Mineo Kaneko, Takayuki Shibata (Japan Advanced Institute of Science and Technology, Japan) |
| Page | pp. 190 - 195 |
| Keyword | rectangular packing, sequence pair, module placement, horizontal/vertical constraint graph |
| Abstract | Repeated placement treated in this paper is the
problem to place multiple copies of a set of modules so that copies
of each module appear repeatedly with a common horizontal
interval Lx and with a common vertical inerval Ly. To identify
the solution space of this repeated placement problem, and
to construct efficient algorithms for treating those placements,
a coding system for those repeated placements of modules is
proposed in this paper. Our proposed coding system uses a
pair of sequences of module names, but one module is allowed
to appear up to twice. By introducing such multiple module
names, our coding system has a potential to describe not only
intra-cycle spatial relation between modules but also inter-cycle
spatial relation. This paper mainly treats semantics and syntax
(feasibility conditions, and decoding algorithm) of our coding
system. |
| Title | LSI Implementation Method of DES Cryptographic Circuit Utilizing Domino-RSL Gate Resistant to DPA Attack |
| Author | *Kenji Kojima, Kazuki Okuyama, Katsuhiro Iwai, Mitsuru Shiozaki (Ritsumeikan University, Japan), Masaya Yoshikawa (Meijyo University, Japan), Takeshi Fujino (Ritsumeikan University, Japan) |
| Page | pp. 196 - 201 |
| Keyword | Side Channel Attack, Differential Power Analysis, Domino-RSL, FPGA, Structured-ASIC |
| Abstract | It is necessary to design the tamper-resistant cryptographic circuit against side-channel attack such as Differential Power Analysis (DPA) to protect the secret key in it. In this paper, we propose the novel Domino-RSL gate primitive, which equalize the output transition probability for any input data using random number. We implemented DES cryptographic circuit using the pseudo Domino-RSL and random masking process on the FPGA board, and the DPA resistance is confirmed experimentally. In addition, we compared the circuit area composed of three kinds of Domino-RSL gates for ASIC implementation. As the result, the S-BOX circuit block using SOP/POS gates shows the smallest area. We estimated the area of DES cryptographic circuit including 8 S-BOX macros, in which SOP/POS gates are arranged by the matrices of 13×8. This area is 1.57 times as large as the normal circuit without DPA countermeasure. |
| Title | The Sizing of Sleep Transistors In Controlling Value Based Power Gating |
| Author | *Lei Chen, Shinji Kimura (Graduate School of Information, Production and Systems, Waseda University, Japan) |
| Page | pp. 202 - 207 |
| Keyword | controlling value, power gating, sleep transistor sizing |
| Abstract | A recently proposed low power technique, controlling-value-based (CV-based) power gating method, has been shown to be an area-efficient
method and is also capable of reducing both dynamic power and leakage power while maintaining the performance of the original circuit. In this paper, we experimentally investigate the issue of sleep transistor sizing in CV-based power gating. Different from
the traditional power gating, sleep transistors can be sized almost the same with the ones used in the original circuit instead of several times larger as usual. The experimental results further proves that CV-based power gating relatively suffers little from the area and delay penalties caused by the sleep transistors compared with other methods. |
| Title | A Verification Method of Pipeline Processing Behavior of Superconducting Single-Flux-Quantum Pulse Logic Circuits |
| Author | *Kazuyoshi Takagi, Motoki Sato, Masamitsu Tanaka (Nagoya University, Japan), Naofumi Takagi (Kyoto University, Japan) |
| Page | pp. 208 - 213 |
| Keyword | Single-Flux-Quantum circuit, logic design verification, pipeline processing, pulse logic |
| Abstract | In pulse-driven synchronous Single-Flux-Quantum (SFQ) logic circuits,
a clock signal is fed to each logic gate.
The behavior of SFQ circuits can be considered as fine-grain
pipeline processing.
Therefore, SFQ circuits must be designed to implement the required
logic functionality, while satisfying the pipeline timing
requirements.
In this paper, we propose a verification method of the pipeline
processing behavior of SFQ circuits.
In the method, we extract timed logic formulae from the circuit, and
check their equivalence to the specification. |
| Title | An Incremental Synthesis Technique for ECO Based on Iterative Procedure for Error Diagnosis and Spare Cell Assignment |
| Author | *Kosuke Watanabe, Hiroto Senzaki, Kosuke Shioki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe University, Japan) |
| Page | pp. 214 - 219 |
| Keyword | ECO, Spare Cell, Error Diagnosis, Incremental Synthesis |
| Abstract | This paper presents an incremental synthesis technique for Engineering Change Orders (ECO’s) based on iterative procedure for error diagnosis and spare cell assignment. A conventional error diagnosis technique based on iterative diagnosis procedure requires many spare cells to rectify a circuit, which causes failure in technology remapping. In order to avoid failure in technology remapping, our technique selects a solution for subcircuits based on available spare cells. Experimental results have shown that our technique improves technology remapping success ratio by 44.4% in average. |
| Title | Error-Rate Prediction for Probabilistic Circuits with More General Structures |
| Author | Mark Lau, *Keck-Voon Ling, Arun Bhanu, Vincent Mooney (Nanyang Technological University, Singapore) |
| Page | pp. 220 - 225 |
| Keyword | probabilistic computing, carry-select adder, error-rate, HSPICE |
| Abstract | A methodology has been proposed recently to predict error-rates of probabilistic circuits having a cascade structure. It was able to predict reasonably accurately for probabilistic ripple-carry and carry-skip adders. The objective of the present paper is twofold. First, the methodology is applied, for the first time in the literature, to a probabilistic carry-select adder, which has a more complex structure than the adders mentioned above. This is to provide additional evidence that the method is versatile and applicable to some non-trivial circuits. Second, the present paper shows that the methodology is also applicable to some seemingly non-cascade circuits. The key technique is to appropriately group circuit components into various blocks before applying the methodology. Such a preprocessing may potentially widen the scope of applicability of the methodology. |