| Title | Increasing Yield Using Partially-Programmable Circuits |
| Author | *Shigeru Yamashita (Ritsumeikan University, Japan), Hiroaki Yoshida, Masahiro Fujita (University of Tokyo, Japan) |
| Page | pp. 237 - 242 |
| Keyword | Partially-Programmable Circuits, Yield, SPFD |
| Abstract | This paper proposes to use a new circuit model called Partially-Programmable Circuits (PPCs) to to increase the yield with very small overhead. PPCs are obtained from conventional logic circuits by replacing their sub-circuits with LUTs. If a connection in an PPC becomes redundant by changing the functionality of some LUTs, the connection is considered to be robust to defects because even if there are some defects at the connection, the circuit works properly by changing the functionality of some LUTs appropriately. To increase the number of such robust connections, we add some redundant connections to LUTs beforehand. We find such redundant connection by using functional flexibility represented by SPFDs and/or CSPFs. Thus, by our proposed approach we can increase the yield by only adding some redundant connections beforehand. From the result of our preliminary experiments, we consider our approach is promising. |
| Title | On Handling Cell Placement with Exclusive Adjacent Symmetry Constraints for Analog IC Layout Design |
| Author | *Shimpei Asano, Kunihiro Fujiyoshi (Tokyo University of Agriculture and Technology, Japan) |
| Page | pp. 243 - 248 |
| Keyword | Symmetry constraint, Sequence-pair, Analog circuits, Placement |
| Abstract | In recent high performance analog IC design, it is often required to place some cells symmetrically to a horizontal or vertical axis. Then, some methods of obtaining the closest placement that satisfies the given symmetry constraints and the topology constraints imposed by a sequence-pair were proposed. But, some cells placed symmetrically are required to be placed nearly. Therefore, in this paper, we define ``exclusive adjacent symmetry onstraint'' and propose a method of obtaining the closest cell placement that satisfies the given constraints. |
| Title | A Low-Cost and Noise-Tolerant ADC BIST with On-the-Fly DNL/INL Calculation |
| Author | Kuo-Yu Chou, Ming-Huan Lu, Ping-Ying Kang, Xuan-Lun Huang, *Jiun-Lang Huang (National Taiwan University, Taiwan) |
| Page | pp. 249 - 253 |
| Keyword | design-for-testability, ADC testing, histogram testing, wireless testing |
| Abstract | A low-cost ADC BIST is developed and implemented in TSMC .18 μm CMOS technology. This design utilizes a noise tolerant code hit counting technique to facilitate the linear histogram testing. In addition, it includes an on-the-fly DNL/INL calcula- tion circuit that makes the pass/fail decision or out- puts the code widths for debugging. This design also possesses an interface compatible with the HOY wire- less testing system. Experiments on a 10-bit pipelined ADC in the HOY environment are performed to vali- date the proposed design. |
| Title | A Four-valude Adder Circuit Design with FG-MOS Transistors |
| Author | *Yuya Wada, Koji Nishi, Akio Shimizu, Sumio Fukai (Saga University, Japan), Yohei Ishikawa (Ariake National College of Technology, Japan) |
| Page | pp. 254 - 259 |
| Keyword | multiple-valued logic, multiple-valued adder, FG-MOS, reduce of circuit area |
| Abstract | In this paper, we designed a four-valued adder circuit with FG-MOSFET. The proposed circuit is an arithmetic logic unit that performs addition four-valued signal mutually on quaternary number. The proposed circuit can reduce for amount of wiring in a chip. The proposed circuit is designed with FG-MOSFET. The FG-MOSFET can achieve the simple circuit configuration and the reduction in the amount of wiring. We confirmed that the proposed circuit can achieve a half circuit aria of binary-valued adder. |
| Title | High-Level Synthesis of 3D IC Designs for TSV Number Minimization |
| Author | Chih-Hung Lee, *Shih-Hsu Huang, Chun-Hua Cheng (Chung Yuan Christian University, Taiwan) |
| Page | pp. 260 - 265 |
| Keyword | High-Level Synthesis, 3D IC, Integer Linear Programming |
| Abstract | Recent progress in manufacturing technology makes it is possible to vertically stack multiple integrated chips. Therefore, developing CAD tools according to characteristics of 3D architecture is urgent and important. In this paper, we propose an integer linear programming formulation to perform signal through-the-silicon-vias (TSV) number minimization in high-level synthesis of 3D ICs. Different from previous works, our formulation directly and accurately minimizes the TSV number. Since TSV number is determined by layer assignment result of communicating resources rather than communicating operations, experimental results promise that our formulation is more effective and accurate on TSV number minimization than previous works. |
| Title | An IEEE 1500 Wrapper Sharing Technique on Reducing Test Cost |
| Author | *Mao-Yin Wang, Ji-Jan Chen (Industrial Technology Research Institute, Taiwan) |
| Page | pp. 266 - 271 |
| Keyword | IEEE 1500, Test Wrapper, Test Scheduling, Sharing, SOC Test Architecture |
| Abstract | Most existing approaches on design of SOC test architectures are developed for test time minimization. In addition to test time, the wrapper cost is also included in the test cost. We propose a test wrapper sharing technique based on the integer linear programming to reduce the wrapper cost. Experimental results show that our technique can achieve at least 24% reduction in wrapper logic and find a test schedule such that the number of WBR cells is minimized. |
| Title | An Incremental Synthesis Technique Based on Error Diagnosis and Technology Remapping for Clusters |
| Author | Hiroto Senzaki, Kosuke Watanabe, Kosuke Shioki, Tetsuya Hirose, Nobutaka Kuroki, *Masahiro Numa (Kobe University, Japan) |
| Page | pp. 272 - 277 |
| Keyword | ECO, Spare cell, Incremental Synthesis, Eror diagnosis |
| Abstract | In an LSI design process, Engineering Change Orders (ECO's) are often given even after the masks have been prepared. This paper presents an incremental synthesis technique based on error diagnosis and technology remapping for clusters in order to reduce the number of spare cells needed to modify the circuit for satisfying functional post-mask ECO's. The proposed technique chooses and modifies not only error locations obtained by error diagnosis, but also clusters such as fanout free regions or reconvergent fanout regions including the error locations if fewer number of spare cells are needed. |
| Title | A Single Layer Trunk Routing Using 45-Degree Lines within Critical Areas for PCB Routing |
| Author | *Kyosuke Shinoda (Tokyo Institute of Technology, Japan), Yukihide Kohira (The University of Aizu, Japan), Atsushi Takahashi (Osaka University, Japan) |
| Page | pp. 278 - 283 |
| Keyword | printed circuit board, plane routing, river routing, routing congestion, 45 degree line |
| Abstract | In Printed Circuit Board (PCB) design, most of routing instances contain congested areas at which routing can not be realized only by horizontal and vertical segments. In this paper, we propose a method that efficiently detects a congested area of single layer PCB routing problems which are derived after escape routing and routing area assignment are finished, and that relaxes routing congestion by locally introducing 45 degree segments so that a feasible routing is efficiently obtained. |
| Title | Clockless Handshaking Inter-chip Communication Applied in Daisy-chained Biomedical Signal Processing SoC |
| Author | *Hong-Hui Chen, Tung-Chien Chen, Cheng-Yi Chiang, Liang-Gee Chen (National Taiwan University, Taiwan) |
| Page | pp. 284 - 289 |
| Keyword | ECG, daisy, chain, daisy-chained, SoC |
| Abstract | In this paper an effective extension interface for connecting a bunch of biomedical SoC is introduced. The interface adopts handshaking mechanism and removes the need to assure synchronization to clock signals which makes the PCB design easier. Payload format is well elaborated and the bus arbitration scheme is updated to make the latencies for doing communication in the SoCs daisy chain minimized in order to provide an effective bandwidth to gather the computational results from chips in the chain. Currently, the designed SoC is targeted to be used in ECG related application. The proposed interface is useful in occasions where on-the-spot ECG signal processing is applied with algorithms that produce computational results at a lower speed than raw data input rate. |
| Title | A New Statistical Maximum Operation for Gaussian Mixture Models Considering Cumulative Distribution Function Curve |
| Author | *Shuji Tsukiyama (Chuo University, Japan), Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 290 - 295 |
| Keyword | Statistical maximum, Gaussian mixture model, Statistical static timing anlalysis |
| Abstract | A new method for the statistical maximum operation of Gaussian mixture models is presented, which is useful in statistical static timing analysis and delay fault testing. The method takes the cumulative distribution function curve into account, and can reduce the error of probability by almost 80% from the previous method. |
| Title | Maximal Resilience for Reliability Enhancement in Interconnect Structure |
| Author | Chih-Yun Pai, *Shu-Min Li (National Sun Yat-sen University, Taiwan) |
| Page | pp. 296 - 301 |
| Keyword | interconnect resilience, interconnect diagnosis, interconnect detection, oscillation ring, fault-tolerant routing |
| Abstract | This paper proposes a resilient scheme to achieve maximal interconnect fault tolerance, reliability and yield for both single and multiple interconnect faults under stuck-at and open fault models. By exploiting multiple routes inherent in a interconnect structure, this scheme can tolerate faulty connections by efficiently finding alternative paths. This scheme is compatible with previous interconnect detection and diagnosis methods, and together they can be applied to implement a robust interconnect structure that may still provide correct communication even under multiple faults. Furthermore, this scheme can identify connections which will cause communication failure if they are faulty. With this knowledge, designers can significantly improve interconnect reliability by augmenting such vulnerable connections. Experimental results show that alternative paths can be found for almost all paths in this scheme; this it provides a way to achieve fault-tolerant and reliability/yield improvement. |
| Title | Minimizing Wirelength and Overflow of 3D-IC Global Routing by Signal-TSV Planning |
| Author | *Guan-Hung Chen, Ke-Ren Dai, Yih-Lang Li (National Chiao Tung University, Taiwan) |
| Page | pp. 302 - 307 |
| Keyword | 3D-IC, TSV, Wirelength, Routing, Planning |
| Abstract | This study integrates signal through-silicon-via (STSV) planning with global routing to eliminate the side-effects of inserting STSVs. The proposed approach mainly comprises two steps: initial STSV positioning places STSVs in appropriate locations and STSV count to each net with the estimation of congested regions; then wirelength-minimization and overflow-reduction issues are addressed by replacing STSVs during global routing. Experimental results show that the proposed method effectively improves the total routed wirelength by 3%~17% and reduces the number of congested regions, below those obtained using state-of-the-art procedures based on 3D-placement benchmarks. Moreover, the results of the proposed STSV-planning approach can reduce the number of DRC-violations and the wirelength by 2%~10%, below those of other methods from the reports of the commercial P&R tool. |
| Title | Bus-Driven Floorplanning With Bus Pin Assignment |
| Author | *Po-Hsun Wu, Tsung-Yi Ho (National Cheng Kung University, Taiwan) |
| Page | pp. 308 - 313 |
| Keyword | Floorplanning, Bus Planning |
| Abstract | With the number of buses increase in multi-core SoC designs, the bus planning problem has become an important factor in determining the performance and power consumption of SoC designs. To ease the effort of bus planning problem, it is desirable to consider this issue in early floorplanning stage. Recently, bus-driven floorplanning (BDF) has attracted much attention in the literature. However, current algorithms adopt an over-simplified formulation which ignores the position and orientation of the bus pins, the simplified formulation may deteriorate the chip performance. In this paper, we propose a BDF algorithm that fully considers the impacts of bus pins. By fully utilizing the position and orientation of bus pins, bus bendings are not restricted to occur at the modules on the bus, thus, it has more flexibilities on the bus shape. With more flexibilities on the bus shape, the size of the solution space is increased and a better BDF solution can be obtained. Compared with the state-of-the-art bus-driven floorplanner, the experimental results show that our floorplanner performs better in runtime by 3.5x, success rate by 1.2x, wirelength by 1.8x, and reduced the deadspace by 1.2x. To enhance the solution quality of our floorplanner, we also develop an algorithm to minimize the wirelength differences between different bits. Experimental results show that our BDF algorithm is very promising. |
| Title | Systematic Yield Optimization for Restricted PPC Pattern Generation with Genetic Algorithm |
| Author | *Katsuhiko Harazaki (Sharp Corporation, Japan), Moritoshi Yasunaga (University of Tsukuba, Japan) |
| Page | pp. 314 - 319 |
| Keyword | DFM, Yield, Lithography, GA, PPC |
| Abstract | Recently, improvements in manufacturing to increase systematic yield have become critical for the development of advanced LSI. To achieve this, studies into Design for manufacturability (DFM) issues have become essential. Normally, discussions about die yield revolved around random yield issues such as defects caused by dust in the fab. However, in the past several years, the discussion has moved to systematic yield including lithography and etching effects which are related to their equipments and manufacturing conditions. To improve die yield and ensure cost effective manufacturing, it is especially important to raise the systematic yield of a process. In this paper, we explain what systematic yield is and describe the relationship between systematic yield and lithography and etching processes. We also investigate various yield models, summarize the relationship between them and then optimize the cell patterns for the Gate Poly layer of a LSI process. Our results show how performing systematic yield optimization of the cell layout pattern taking into account Process and proximity compensation (PPC) can be achieved with a Genetic Algorithm methodology. |
| Title | Clock Planning for Multi-Voltage and Multi-Mode Designs |
| Author | *Chang-Cheng Tsai, Tzu-Hen Lin, Shin-Han Tsai, Hung-Ming Chen (National Chiao Tung University, Taiwan) |
| Page | pp. 320 - 324 |
| Keyword | clock planning, multi-voltage, low power |
| Abstract | Low power demand drives the development of lower power design architectures, among which multiple supply voltage is one of the state-of-the-art techniques to achieve low power. In addition, dynamic voltage frequency scaling and adaptive voltage scaling are popular power saving techniques during chip operation to provide different modes for various performance requirements. It is therefore very challenging to generate a clock tree for different operation modes. This paper proposes several implementations on this important issue, one of which can provide smallest clock latency and minimum clock skew on average of required operation modes in multi-voltage designs. |
| Title | Efficient Random-Defect Aware Layer Assignment and Gridless Track Routing |
| Author | *Yu-Wei Lee, Yen-Hung Lin, Yih-Lang Li (National Chiao Tung University, Taiwan) |
| Page | pp. 325 - 330 |
| Keyword | Design for yield, random defect, griless design, track routing, layer assignment |
| Abstract | Design for yield (DFY) problems have received increasing attention. Of particular concern in DFY problems is how to formulate and reduce a critical area for random defects. Arranging interconnections is recognized as an effective means of improving the sensitivity towards random defects. Previous works have demonstrated that random defects significantly influence interconnections and the effectiveness of layer assignment and track routing to enhance routing quality and performance. This work proposes a random defect aware layer assignment and gridless track routing (RAAT) to eliminate the effect of random defects. Gridless track routing comprises wire ordering, wire sizing and spacing in this work. Exposure ratio metric is proposed to assign well each iroute to a specific layer. RAAT utilizes min-cut partitioning, a conventionally adopted method for placement and floorplanning, to place interconnections. Slicing tree-based structure improves the efficiency of wire ordering in lowering overlapped length between adjacent partitions. Finally, a second-order cone programming refined by considering an extra random-defect effect determines the position and width of each iroute. Experimental results demonstrate the necessity of the integration of layer assignment and track routing. Results further demonstrate the effectiveness of the gridless track routing methods proposed by RAAT. In addition to finishing each case more rapidly with higher completion rate than previous works do, RAAT reduces up to 20% of the number of failures in the Monte Carlo simulation as compared to previous works. |
| Title | Analog Layout Generation based on Wiring Symmetry |
| Author | *Yu-Ming Yang, Iris Hui-Ru Jiang (National Chiao Tung University, Taiwan) |
| Page | pp. 331 - 336 |
| Keyword | Analog design automation, wiring symmetry |
| Abstract | Unlike the mature and highly automatic flow for digital layout generation, the existing method to generate an analog layout is far from automatic because it highly depends on the designer’s expertise. Prior endeavors are mainly dedicated to analog placement because they consider only the device symmetry constraint. This paper raises the wiring symmetry issue to analog layout: wiring symmetry is as crucial as device symmetry. Hence, we propose an analog placement and global routing algorithm to consider both types of symmetry constraints. During placement, we utilize the device folding technique to enhance the flexibility and feasibility on symmetry. Our results show that our algorithm can produce a promising initial layout to speed up the analog design process. |
| Title | An Approach for Computation Efficiency Improvement of Power Grid Simulation by GPGPU |
| Author | *Makoto Yokota, Yuuya Isoda, Tetsuya Hasegawa, Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 337 - 342 |
| Keyword | GPGPU, Simulation, Power Grid |
| Abstract | This paper proposes a speeding up technique for massively parallel power grid simulator by GPGPU (General Purpose computing on Graphics Processing Unit). The proposed power grid simulator is implemented by considering the GPU architecture. Experimental result show that the proposed method realizes 2.9 times faster than the conventional method. As a result, the proposed power grid simulator has achieved 75 times speeding-up than CPU computation with same accuracy. |