| Title | A Formal Full Bus TLM Modeling for Fast and Accurate Contention Analysis |
| Author | *Mao-Lin Li, Chen-Kang Lo, Li-Chun Chen (National Tsing Hua University, Taiwan), Hong-Jie Huang, Jen-Chieh Yeh (Industrial Technology Research Institute, Taiwan), Ren-Song Tsay (National Tsing Hua University, Taiwan) |
| Page | pp. 147 - 152 |
| Keyword | bus modeling, arbiter, TLM |
| Abstract | This paper presents an effective Cycle-count Accurate Transaction level (CCA-TLM) full bus modeling and simulation technique. Using the two-phase arbiter and master-slave models, an FSM-based Composite Master-Slave-pair and Arbiter Transaction (CMSAT) model is proposed for efficient and accurate dynamic simulations. This approach is particularly effective for bus architecture validation and contention analysis of complex Multi-Processor System-on-Chip (MPSoC) designs. The experimental results show that the proposed approach performs 23 times faster than the Cycle-Accurate (CA) bus model while maintaining 100% accurate timing information at every transaction boundary. |
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| Title | A Formal Approach to Designing Arithmetic Circuits over Galois Fields Using Symbolic Computer Algebra |
| Author | *Kazuya Saito, Naofumi Homma, Takafumi Aoki (Tohoku University, Japan) |
| Page | pp. 153 - 158 |
| Keyword | arithmetic circuits, formal verification, galois field, computer algebra |
| Abstract | This paper proposes a formal approach to designing arithmetic circuits over Galois Fields (GFs). Our method represents a GF arithmetic circuit by a hierarchical graph strucuture specified by variables and arithmetic formulae over GFs. The proposed circuit description is applicable to any GF(pm) (p ≥ 2) arithmetic and is formally verified by symbolic computation techniques such as polynomial reduction using Groebner basis. In this paper, we propose the graph representation and show some examples of its description and verification. The advantageous effect of the proposed approach is demonstrated through experimental designs of parallel multipliers over Galois field GF(2m) for different word-lengths and irreducible polynomials. An inversion circuit consisting of some multipliers is also designed and verified as a further application. The result shows that the proposed approach has a definite possibility of verifying practical GF arithmetic circuits where the conventional simulation and verification techniques failed. |
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| Title | Optimal Design of Allpass Digital Filters using Artificial Bee Colony |
| Author | *Wei-Der Chang (Department of Computer and Communication, Shu-Te University, Taiwan), Shing-Tai Pan (Department of Computer Science and Information Engineering, National University of Kaohsiung, Taiwan), Kuo-Hua Cheng, Ming-Chieh Hsu (Department of Computer and Communication, Shu-Te University, Taiwan) |
| Page | pp. 159 - 162 |
| Keyword | all-pass digital filter, phase response, artificial bee colony |
| Abstract | This paper applies a novel artificial bee colony algorithm to solve the design problem of allpass digital filters. We wish that the phase response of allpass filter can meet the desired specification. To achieve this aim, the ABC algorithm is utilized to update the related filter coefficients such that certain cost function of the algorithm can be minimized as possible as much. Finally, numerical simulation results will demonstrate the feasibility and effectiveness of the proposed scheme. |
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| Title | A Processor Architecture for Multi-Dimensional Parity Check Code Processing |
| Author | *Ryota Endo (Osaka University, Japan), Hiroki Ohsawa (Fuji Xerox Co., Ltd, Japan), Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka University, Japan) |
| Page | pp. 163 - 167 |
| Keyword | Low Energy, ASIP, Error Correcting Code, MDPC |
| Abstract | Multi-Dimensional Parity Check (MDPC) code is an error correcting code which has been widely used for wireless communications under low error rate environment. In this study, a low-power processor for MDPC code processing is introduced and evaluated. Through experimental results, the processor achieves about 90% lower in energy consumption compared with an implementation by a usual RISC processor. |
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| Title | Application on the Hardware/Software Co-simulator; Implementation of Multi-stage, Multi-rate 2-D filter |
| Author | *Yukiko Takanishi (Faculty of System Design Tokyo Metropolitan University, Japan), Yuichi Nakamura (System IP Core Research NEC Corporation, Japan), Takao Nishitani (Faculty of System Design Tokyo Metropolitan University, Japan) |
| Page | pp. 168 - 173 |
| Keyword | hardware/software co-simulation, FPGA, Simulink, visual debugging, FIR implementation |
| Abstract | A functional expansion of a hardware-software co-simulator, using “Simulink” on PC and an FPGA emulator board, is realized for the purpose of real-time HDTV signal processing. In the proposed co-simulator, the emulation is carried out by using a set of raster scanning data processing, instead of the frame-based processing which is suitable for processing “Simulink” block. In addition, a visual verification approach in terms of processing delay between Simulink blocks is introduced for adjusting the connection of these blocks within the emulator. |
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| Title | Checkpoint Selection for DEPS Framework Based on Quantitative Evaluation of DEPS Profile |
| Author | *Hirotaka Kawashima, Gang Zeng, Hideki Takase, Masato Edahiro, Hiroaki Takada (Nagoya University, Japan) |
| Page | pp. 174 - 179 |
| Keyword | DEPS, energy optimization, DVFS, checkpoint |
| Abstract | A dynamic energy performance scaling (DEPS) framework had been proposed as a generalization of the dynamic voltage frequency scaling (DVFS). In this paper, we propose a scheme of checkpoint selection for DEPS framework. The checkpoint is a sequence of operations for switching the hardware configurations. Our scheme of checkpoint selection judges energy efficiency of a checkpoint set using intra-task analysis informations. Our scheme evaluates DEPS profiles related with different checkpoint sets, and determines which checkpoint set is the most energy efficient. To achieve this scheme, we also propose a quantitative evaluation method of the DEPS profile. This method enables us to judge which DEPS profile is the most energy efficient. From experimental results, we confirm the reasonability of our quantitative evaluation, and that our scheme can select the optimal checkpoint set in realistic time. |
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| Title | Model-Based Generation of a Fast and Accurate Virtual Execution Platform for Software-Intensive Real-Time Embedded Systems |
| Author | *Jochen Zimmermann, Martin Küster, Oliver Bringmann (FZI Karlsruhe, Germany), Wolfgang Rosenstiel (Universität Tübingen, Germany) |
| Page | pp. 180 - 185 |
| Keyword | Early System Verification, SystemC, Timing Simulation, Power Simulation, Model-based Generation |
| Abstract | The shift towards embedded functionality increasingly realized in software and the permanently growing complexity in design and verification require new methodologies in the development process of software-intensive real-time embedded systems. Major issues related to the software and hardware architecture have to be found out as early as possible to reduce subsequent costs and to allow a short time-to-market. Therefore, system analysis and verification must be possible in every stage during the design process. In this paper, we present an approach to generate a virtual execution platform in SystemC which allows to execute embedded software with strict consideration of the underlying hardware platform configuration. Starting from abstract UML/SysML models of software and hardware architecture or/and abstraction of legacy code, model transformation techniques are used during the generation process. In combination with source code timing annotations obtained from binary code analysis this approach allows a fast and accurate simulation of the embedded system model. To substantiate our allegation we present experimental results from different application domains. |
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| Title | Model Based Parallelization from the Simulink Models and Their Sequential C Code |
| Author | *Takahiro Kumura (Osaka University/NEC Corporation, Japan), Yuichi Nakamura (NEC Corporation, Japan), Nagisa Ishiura (Kwansei Gakuin University, Japan), Yoshinori Takeuchi, Masaharu Imai (Osaka University, Japan) |
| Page | pp. 186 - 191 |
| Keyword | model, dataflow, pipeline, parallelization, multicore |
| Abstract | This paper proposes a method to generate parallel C codes suited to pipeline processing from models developed on the Simulink. This paper focuses on a pipeline processing based on a way of applying the theory of communicating sequential processes. Under the parallelization process, the proposed method eliminates loop structures in models and builds directed acyclic graphs suited to a pipeline processing. On an experiment, the proposed method reduces the execution time to 26.3% on a 4-core processor. |
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| Title | Saving Power Consumption in Final Stage Adder of Multiplier By Using Difference in Arrival Times with Input Signals |
| Author | *Yuzuru Shizuku, Takeshi Kogure, Tatsuya Fujioka, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe University, Japan) |
| Page | pp. 192 - 196 |
| Keyword | multiplier, low power comsumption, carry absorbing circuit |
| Abstract | In general, a Final Stage Adder (FSA) at the final stage of a multiplier is composed of a high-speed adder for shorter delay time. However, employing such a high-speed adder without paying attention to the difference in the arrival times with input signals increases the circuit size and power consumption due to unnecessary signal transitions. In this paper, we propose a technique for saving power consumption in the FSA based on a circuit architecture using difference in arrival times with input signals. Simulation results have shown that the proposed circuit reduces power consumption by 9% and power-delay product (PDP) by 12% compared with a conventional APPNA-based circuit. |
| Title | A Technique for SAT-based Test Generation through History of Reusing Solutions |
| Author | *Kenji Ueda, Fumiyuki Hafuri, Toshiya Mukai, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City University, Japan) |
| Page | pp. 197 - 198 |
| Keyword | Boolean satisfiability, Test generation, Solution reuse, History of reusing, Instance similarity |
| Abstract | This paper presents a technique for test pattern generation (TPG) based on Boolean satisfiability (SAT) in a situation where a solution to a SAT instance is reused as the initial truth assignment for solving the successive instance. The efficiency of obtaining a solution to it depends on the order in reusing each variable of the previous solution one by one. The proposed technique utilizes the history of reusing solutions representing whether each variable of previous solutions is successfully reused. Experimental results show that the proposed technique using such a history is effective in test generation time. |
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| Title | Reconfigurable Cells for Post-Mask ECO |
| Author | *Hiroto Senzaki, Tomoki Matsuyama, Kosuke Watanabe, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe University, Japan) |
| Page | pp. 199 - 204 |
| Keyword | Engineering change order (ECO), Reconfigurable (RECON) cell, Spare cell, Incremental synthesis |
| Abstract | In an LSI design process, Engineering Change Orders (ECOs) are often given even after the masks have been prepared. Spare-cell rewiring is a popular technique for post-mask ECO. In contrast to conventional spare cells having only one type of logic function, a reconfigurable (RECON) cell can be configured as one of three types of functional cells such as inverter, NAND, and NOR. This paper presents two new types of RECON cells: 2T-RECON cell and 6T-RECON cell with more types of logic functions. Technology remapping using the proposed RECON cells reduces the number of cells needed to complete post-mask ECO compared with using conventional spare cells. Experimental results with benchmark circuits have shown that the RECON cell rewiring scheme completes functional ECO with about 28% fewer cells than spare-cell rewiring. |
| Title | GPU Acceleration of Cycle-based Soft-Error Simulation for Reconfigurable Array Architectures |
| Author | *Takashi Imagawa, Takahiro Oue, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto University, Japan) |
| Page | pp. 205 - 210 |
| Keyword | GPGPU, cycle-based simulation, soft error, coarse-grained reconfigurable array |
| Abstract | In this paper, we propose two methods for accelerating cycle-based soft-error simulation of coarse-grained reconfigurable arrays (CGRAs) using GPUs. Two implementation strategies depending on the size of target CGRA is proposed considering struc- tural regularities of CGRA and memory architecture of GPUs. One of the proposed method achieves up to 68.0 times acceleration for small-scale CGRAs, while the other achieves 15.3 times acceleration on the av- erage without limitation on the size of CGRA. |
| Title | Heterogeneous Assertion-Based Verification for Medical Devices Development |
| Author | Stefan Lämmermann (Universität Tübingen, Germany), Lukas Pielawa (OFFIS, Germany), *Andreas Burger (FZI Forschungszentrum für Informatik an der Universität Karlsruhe, Germany), Jan Schlemminger (OFFIS, Germany), Jürgen Ruf, Thomas Kropf (Universität Tübingen, Germany), Andreas Hein (OFFIS, Germany), Wolfgang Rosenstiel (Universität Tübingen, Germany) |
| Page | pp. 211 - 216 |
| Keyword | assertion based verification, hetereogenous system simulation, medical device development, formalization of medical requirements |
| Abstract | This paper describes the employment of an assertion-based verification methodology in the early stage of medical device development. The utilization of MSAL verification process enables to translate the medical characteristics automatically into observer automata for monitoring the systems behaviour. The experimental results show the integration of medical characteristics as assertions into simulation of a medical device in Matlab/Simulink and demonstrate the broad applicability and the high value of the evolved solution. |
| Title | Degradation of Oscillation Frequency of Ring Oscillators Placed on a 90 nm FPGA |
| Author | *Shouhei Ishii, Kazutoshi Kobayashi (Kyoto Institute of Technology, Japan) |
| Page | pp. 217 - 221 |
| Keyword | NBTI, FPGA, Variation, Degradation |
| Abstract | We focus on degradation of FPGAs which has become dominant due to scaling and quantitatively estimate the degradation of FPGAs by NBTI. We map ring oscillators on the Cyclone II FPGAs and measure the variation of oscillation frequency. In the result, the variation of oscillation frequency is 2.46%. As for degradation of FPGAs, we measure degradation of oscillation frequency until 10,000 seconds passed at room temperature (28Ž), 80Ž and 100Ž. As the result, degradation of oscillation frequency increases as temperature increases and degradation of about 0.1% at 10,000 seconds is observed at high temperature. |
| Title | NUMANA: A Hybrid Numerical and Analytical Thermal Simulator for 3-D ICs |
| Author | Yu-Min Lee, Tsung-Heng Wu (National Chiao Tung University, Taiwan), Pei-Yu Huang (Industrial Technology Research Institute, Taiwan), *Chi-Wen Pan (National Chiao Tung University, Taiwan) |
| Page | pp. 222 - 226 |
| Keyword | 3-D IC, thermal simulation |
| Abstract | This paper provides a hybrid framework by using numerical and analytical simulation techniques, NUMANA, to estimate the temperature profile of 3-D IC. Compared with a well known commercial tool, ANSYS, its error is within [-0.75%, 0.88%]. Furthermore, comparing with a fast modified-nodal-analysis thermal solver for a thermal circuit with 40K nodes, NUMANA can accurately estimate the temperature profile of 3-D IC with 3212.3X efficiency improvement. |
| Title | 2-Stage Simulated Annealing with Crossover Operator for 3D-Packing Volume Minimization |
| Author | *Yiqiang Sheng (Tokyo Institute of Technology, Japan), Atsushi Takahashi (Osaka University, Japan), Shuichi Ueno (Tokyo Institute of Technology, Japan) |
| Page | pp. 227 - 232 |
| Keyword | 3D packing, 2-stage simulated annealing, sequence-k-tuple representation, VLSI physical design, CAD technique |
| Abstract | The 3D packing for VLSI physical design is facing big challenges to get better solution quality with less computational time. In this paper, we propose 2-stage simulated annealing with crossover operator (2-SA-X) to solve a general rectangular 3D-packing problem by using sequence-k-tuple representation, where k is defined by 3 and 5. The basic ideas of this research are to reuse the information of past solution by integrating the crossover operator from genetic algorithm and to improve the global search ability by using two different stages. The first stage mainly focuses on the global search by moving methods with big changes, including the crossover, while the second stage focuses on local search by the moving methods with small changes. Based on the experiment using ami98_3D benchmark, the computational performance of 3D packing is considerably improved. The paper shows how much the 3D-packing ratio of volume and the computational time can be improved by using the proposed 2-SA-X algorithm, comparing with normal 2-stage simulated annealing (2-SA) without the crossover operator. |
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| Title | Thermal Analysis for 3-D ICs Considering Interconnect Power Estimation |
| Author | *Chi-Wen Pan, Ying-Hsiang Liu, Yu-Min Lee (National Chiao Tung University, Taiwan), Pei-Yu Huang (Industrial Technology Research Institute, Taiwan), Chi-Ping Yang (National Chiao Tung University, Taiwan) |
| Page | pp. 233 - 238 |
| Keyword | 3D, IC, Thermal, Interconnect, Power |
| Abstract | This work presents a 3-D IC thermal simulator based on table look-up techniques, which considers the thermal effect of interconnect power. The key advantages are that the proposed simulator can fast analyze and incrementally update the temperature profile for thermal-aware physical design procedures. With delivering the portion of power into interconnect, the maximum temperature difference is about 2.4% comparing with the thermal simulation, which is set the total power as gate power. |
| Title | Net-based Move in SA-based Placement for a Switch-Block-Free Reconfigurable Device |
| Author | *Masato Inagi, Masatoshi Nakamura, Tetsuo Hironaka (Hiroshima City University, Japan), Takashi Ishiguro (Taiyo Yuden Co., Ltd., Japan) |
| Page | pp. 239 - 240 |
| Keyword | placement, MPLD, FPGA, move |
| Abstract | In this paper, we propose an enhanced SA-based placement algorithm for a switch-block-free reconfigurable architecture, introducing a move function that shifts all the logic cells which belong to a randomly selected net to the same direction. Although neighbor solutions generated by the move function are similar to the current solution, iteration of straightforward move functions that move a single logic cell at a time rarely generates such a solution. The move function improves reachability between good solutions, and thus improves the quality of the final solution. |
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| Title | A Nonlinear Optimization Methodology for Resistor Matching in Analog Integrated Circuits |
| Author | *Sheng-Jhih Jiang, Tsung-Yi Ho (National Cheng Kung University, Taiwan) |
| Page | pp. 241 - 246 |
| Keyword | Analog CAD, Layout, Resistor Matching |
| Abstract | In analog design flow, one of the most important issues is to achieve accurate resistor ratios during the layout phase, which is called resistor matching. In the literature, researchers have proposed several methodologies achieving high matching quality in a rectangular structure. However, under the fixed-outline constraint, layout designers will place normal blocks such as macros and intellectual properties (IPs) first and then place the resistors. But the remaining space for resistors is usually rectilinear rather than rectangular, which is not appropriate for achieving high matching quality. To overcome this problem, we propose a nonlinear optimization methodology for globally improving the matching quality. Our algorithm enhances the matching quality by deforming the rectilinear shape into centrosymmetrical shape and simultaneously minimize the perturbation of the pre-placed normal blocks. Experimental result shows that the proposed algorithm is very promising. |
| Title | Precise Expression of nm CMOS Variability with Variance/Covariance Statistics on Ids(Vgs) |
| Author | *Koutaro Hachiya (Jedat, Inc., Japan), Hiroo Masuda (ChiHiro Consultant, Japan), Atsushi Okamoto (Fujitsu Semiconductor Ltd., Japan), Masatoshi Abe, Takeshi Mizoguchi (Toshiba I.S. Corp., Japan), Goichi Yokomizo (STARC, Japan) |
| Page | pp. 247 - 252 |
| Keyword | model parameter extraction, statistical MOSFET model |
| Abstract | We have measured the drain current (Ids) variation of various sized MOS transistors under different gate bias conditions (Vgs). Both variation sigma (standard deviation) of Ids and correlations among Ids, Vth and Gm are considered to play important role in accurate expression of the device/circuit performance variations. This paper provides accurate model parameter extraction method considering size and bias dependence of the sigma and the correlations. |
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| Title | A Transistor-level Symmetrical Layout Generation for Analog Device |
| Author | *Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (The University of Kitakyushu, Japan) |
| Page | pp. 253 - 257 |
| Keyword | analog layout, symmetrical placement, symmetrical routing, diffusion sharing |
| Abstract | This paper introduces a transistor-level symmetrical layout generation algorithm aiming at maximum diffusion-merging to the current paths for analog circuit. We present a SA-based algorithm to symmetrically assign the transistor pair into two rows and meanwhile minimize the total wirelength and diffusion gaps. Two examples are used to demonstrate the effectiveness of our algorithm. |
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| Title | LDPC Coded MIMO Communication System With Relay Selection |
| Author | *Nanfan Qiu, Xiao Peng, Yichao Lu, Satoshi Goto (Waseda University, Japan) |
| Page | pp. 258 - 261 |
| Keyword | LDPC, MIMO, Relay |
| Abstract | This paper presents a low-density parity check(LDPC) coded multiple-input multiple- output(MIMO) cooperative communication system with relay selection strategy. In the proposed co- operative network with multiple potential relays, we present selection cooperation to choose the best re- lay. We also present the outage probability analysis of this system. Furthermore, in the proposed archi- tecture relays rstly perform sphere detection, then send extrinsic messages to the terminal node by using space time block codes. By this architecture the ter- minal node only needs to perform LDPC decoding so the power consumption of the terminal node can be reduced. |
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| Title | Subkey Driven Power Analysis Attack in Frequency Domain against Cryptographic LSIs |
| Author | *Ryusuke Satoh, Daisuke Matsushima, Masaya Yoshikawa (Meijo University, Japan) |
| Page | pp. 262 - 267 |
| Keyword | Side-channel attacks, Power analysis, CPA, Frequency domain, AES |
| Abstract | For cryptographic LSI implemented on IC cards, it is important to secure resistance against power analysis attacks. This study proposes a new power analysis attack method that can be used to improve the efficiency of the resistance evaluation of cryptographic LSI. Compared with resistance evaluation that uses typical attack methods, the proposed method reduces the computational amount required for resistance evaluation greatly while maintaining the attack accuracy. In this study, the validity of the proposed method is verified through evaluation experiments performed with the use of a cryptographic circuit implemented on FPGA. |
| Title | Realtime Mixed Reality Representation with a Virtual Light Source based on a Mobile 3D Acquisition |
| Author | *Yoji Watatani (Graduate School of Engineering, Kansai University, Japan), Yoshihiro Yasumuro, Hiroshige Dan, Masahiko Fuyuki (Faculty of Environmental and Urban Engineering, Kansai University, Japan) |
| Page | pp. 268 - 271 |
| Keyword | mixed reality, calibration, TOF camera, superposition, real time |
| Abstract | Mixed reality (MR) has gathered attention recently as an effective technique for overlaying computer-generated virtual objects on physical scenes. Using MR, this research proposes a realtime imaging system to produce visual illumination effects on physical objects with a virtual light source. The proposed system models the shapes and the color information of a real scene through a realtime process. The illumination influenced by the virtual light source on the scene model are superposed on an actual video image to create MR representation. Experimental results show virtual light-up effects on the physical shapes and colors of the real objects by setting up a non-existing lighting configurations. |
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| Title | A Full Dynamically Reconfigurable Vision-chip System Including a Lens-array |
| Author | *Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito (Shizuoka University, Japan) |
| Page | pp. 272 - 277 |
| Keyword | Vison Chips, FPGA, ORGA, Image sensor |
| Abstract | Recently, for use in autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. However, to recognize many images quickly with such systems, many template images must be read out dynamically from memory. They must then be sent to a processor quickly. Realizing such high-speed real-time image recognition operation is difficult because of a bottleneck of transfer speed between the memory and the processor. Therefore, to improve the bottleneck, this paper experimentally presents a full dynamically reconfigurable vision-chip system including a lens-array. |
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| Title | Improved Region-Growing Image-Segmentation Algorithm Using Dynamic Connection Weight Calculation Based on Mean Value of Exited Pixels |
| Author | *Naotaka Kawakami, Ryosuke Kimura, Tatsuya Sugahara, Tetsushi Koide, Hans Jürgen Mattausch (Hiroshima University, Japan) |
| Page | pp. 278 - 283 |
| Keyword | Image segmentation, Dynamic connection weight |
| Abstract | This paper presents an image segmentation algorithm which uses a connection weight-based region-growing algorithm.By using a dynamic method which adjusts the connection weights to neighboring pixels based on mean values of exited pixels during the growth process, we enable segmentation of an image object with indistinct boundaries. In this paper, we introduce the proposed region-growing algorithm, and present the evaluation results with MATLAB. |
| Title | An Accurate Pedestrian Detection Utilizing Feature of Partitioned Image by Color |
| Author | Masashi Ide, *Masataka Takahashi, Yoshiya Sugita, Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 284 - 289 |
| Keyword | Intelligent transportation systems, pedestrian detection, outline tracing |
| Abstract | Our approach aims at spreading the pedestrian recognition technique not only for luxury cars but also for general vehicles. Therefore, we propose an algorithm not for a stereo camera but for a cheap simple eye camera of cost. It traces outline of the target by a multiplex approach, in a grayscale and several partitioned domains of the hue of color. This technique provides several new techniques, a method of efficient enlargement of extracted edge image, a characterization method to analyze the angle histogram of outline tracing, and a composition method of multiplex ROI's. In candidates of the outlines of the body or the dress, the most likely ones are extracted. Highly precise recognition result was obtaine |
| Title | A Fast and Accurate Algorithm for Traffic Sign Recognition |
| Author | Yoshiya Sugita, *Yuuki Tomisawa, Masashi Ide, Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 290 - 295 |
| Keyword | traffic sign recognition, inteligent transportation system |
| Abstract | Image recognition technology is an important role for drivers. Especially traffic sign recognition is one of useful technology and researched many researchers. In this paper, traffic signs are recognized by an internal area of traffic signs and numbers of its areas. This paper proposes two features: an internal area of traffic signs and numbers of its areas for recognition of traffic signs are used to recognize a proper traffic sign. Although TRR (Total Recognition Rates) is not so much high due to miss of detection step, the recognition step accomplished recognition of 94%. With these methods, high accuracy is proved in the recognition step. Moreover, this method's calculation is six times as fast as template matching which is representative method in the traffic sign recognition technology. |