| Title | Place-and-Route Algorithms for a Reliability-Oriented Coarse-Grained Reconfigurable Architecture Using Time Redundancy |
| Author | *Takashi Imagawa, Masayuki Hiromoto (Kyoto University, Japan), Hiroshi Tsutsui (Hokkaido University, Japan), Hiroyuki Ochi (Ritsumeikan University, Japan), Takashi Sato (Kyoto University, Japan) |
| Page | pp. 76 - 81 |
| Keyword | coarse-grained reconfigurable architecture, reliability, time redundancy, dynamic reconfiguration, place-and-route algorithm |
| Abstract | Coarse-grained reconfigurable architectures (CGRAs)
are expected to enhance the reliability of LSI systems.
The time-redundancy technique can enhance the fault tolerance
even under severe circuit area constraints.
This paper proposes two place-and-route algorithms for the CGRA that utilizes time-redundancy.
The application circuits implemented on the CGRA with these algorithms are different
in the performance degradation and hard-error tolerance.
The one algorithm can achieve the hard-error tolerance improvement with small performance degradations,
the other improves the tolerance largely with large degradations. |
| Title | Power Analysis Resistant IP Core Using IO-Masked Dual-Rail ROM for Easy Implementation into Low-Power Area-Efficient Cryptographic LSIs |
| Author | *Megumi Shibatani, Mitsuru Shiozaki, Yuki Hashimoto, Takaya Kubota, Takeshi Fujino (Ritsumeikan University, Japan) |
| Page | pp. 82 - 87 |
| Keyword | cryptographic module, side-channel attack, power analysis, countermeasure circuit, IO-masked dual-rail ROM |
| Abstract | Recently, it has been pointed out that power analysis (PA) attacks are a threat to cryptographic circuits which handle confidential information. Our goal of this study is to provide easily implementable cryptographic IP core in small area and low power consumption with PA resistance. We have proposed IO-masked dual-rail ROM scheme and prototyped an advanced encryption standard (AES) circuit using the proposed scheme. This paper presents the evaluated results of chip area, power consumption, and PA resistance. |
| PDF file |
| Title | Scaling up Size and Number of Expressions in Random Testing of Arithmetic Optimization of C Compilers |
| Author | Eriko Nagai (Fujitsu Systems West Limited, Japan), *Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin University, Japan) |
| Page | pp. 88 - 93 |
| Keyword | compiler, random testing, programming language C |
| Abstract | This paper presents an enhanced method of
testing validity of arithmetic optimization of C compilers using
randomly generated programs. Its bug detection capability is
improved over an existing method by 1) generating longer arithmetic
expressions and 2) accommodating multiple expressions in test
programs. Undefined behavior in long expressions is successfully
avoided by modifying problematic subexpressions during computation
of expected values for the expressions. An efficient method for
minimizing error inducing test programs is also presented, which
utilizes binary search. Experimental results show that a random
test system based on our method has higher bug detection capability
than existing methods; it has detected more bugs than previous
method in earlier versions of GCCs and has revealed new bugs in the
latest versions of GCCs and LLVMs. |
| PDF file |
| Title | A Routing Method Using Minimum Cost Flow Algorithm for Routes with Target Wire Lengths |
| Author | *Kunihiro Fujiyoshi, Kazuo Yamane (Tokyo University of Agriculture and Technology, Japan) |
| Page | pp. 94 - 99 |
| Keyword | routing, PCB, error, minimum cost flow algorithm |
| Abstract | Due to the increase of operation frequency, influence of routing delays is increasing.
So it is important to obtain the routes with the small difference between target wire length and actual wire length.
For this purpose, CAFE router which obtains the river routing with small length error using maximum flow was proposed.
But, in many cases, the obtained routes have small length error.
In this paper, we propose a method using minimum cost flow, which obtains routes with smaller differences. |
| Title | Compact Pipeline Hardware Architecture for Pattern Matching on Real-Time Traffic Signs Detection |
| Author | *Anh-Tuan Hoang, Mutsumi Omori, Masaharu Yamamoto, Tetsushi Koide (Hiroshima University, Japan) |
| Page | pp. 100 - 105 |
| Keyword | Traffic signs detection, Pipeline Architecture, Compact Hardware |
| Abstract | This paper describes a novel compact hardware oriented algorithm and its conceptual implementation for real-time traffic signs detection system. The limit speed sign area on a grayscale video frame is detected based on a novel, simple and compact rectangle pattern matching and circle detection modules. The limit speed recognition system is divided into two-pipeline stages. The frame is scanned with multi-scan windows in parallel for each position and each scan windows is also processed in pipeline to increase throughput. It achieve 100% in detection rate. |
| PDF file |
| Title | Rover II: A Router for Via Configurable Structured ASIC with Standard Cells and IPs |
| Author | Chiung-Chih Ho, Hsin-Pei Tsai, *Rung-Bin Lin (Yuan Ze University, Taiwan) |
| Page | pp. 114 - 117 |
| Keyword | Structured ASIC, Router, Regular fabric, IP |
| Abstract | This article presents a router, called Rover II, for via-configurable structured ASIC. Rover II extends the work of Rover to handle IPs and incorporate a porting of NTHU-route 2.0 and NCTU-GR global routers. Experimental results show that Rover II can successfully route a via-configurable structured ASIC with standard cells and IPs under different routing fabrics. The results also show that the global router in Rover is as good as the state-of-art global routers such as NTHU2.0 and NCTU-GR. |
| Title | A Compact and Energy-Efficient Muller C-Element for Low-Voltage Asynchronous CMOS Digital Circuits |
| Author | *Yuzuru Shizuku, Tetsuya Hirose, Yuya Danno, Nobutaka Kuroki, Masahiro Numa (Kobe University, Japan) |
| Page | pp. 118 - 122 |
| Keyword | low supply voltage, asynchronous circuit, Muller-C-element, energy-efficient |
| Abstract | An asynchronous circuit has attracted much attention as a promising low-power and robust digital design technique. Muller C-element is one of the fundamental building blocks for asynchronous circuit and is used in timing control of each circuit block and pipeline processing. However, conventional Muller C-elements have the problem that it is difficult to operate at lower supply voltage. In this paper, we propose a new Muller C-element capable with low supply voltage operation. The circuit is based on the conventional C-element and use a MOS resistor to ensure robust operation. Simulation results have demonstrated that the proposed circuit can operate at low-supply voltage of 0.38 V and the power-delay product (PDP) was 4.32 aJ at VDD = 1.08 V, which was lower by 9.3% compared with a conventional Muller C-element. |
| Title | Analytical Thermal Modeling and Calibration Method for Lithium-Ion Batteries |
| Author | *Keiji Kato, Yusuke Yamamoto, Naoki Kawarabayashi, Lei Lin, Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 123 - 128 |
| Keyword | Lithium-ion battery, Thermal analysis, Calibration |
| Abstract | Lithium-ion battery is an important component to
construct the circuit of mobile systems. However, the behavior
of the battery varies depending on its thermal condition. Thus,
to optimize the mobile system, in terms of long life and low
power, it is important to estimate the inner temperature of the
battery. This paper proposes an analytical method to estimate
the inner temperature considering Joule heat and Entropy heat.
Evaluation by a real battery sample is also shown. |
| Title | A Sensor Modeling Technique Using SystemC-AMS For Fast Simulation of System-in-Package Based Bio-Medical Systems |
| Author | *Arif Ullah Khan, Yoshinori Takeuchi, Masaharu Imai (Osaka University, Japan) |
| Page | pp. 129 - 133 |
| Keyword | Sensor, Bio-Medical, Simulation Model, SystemC-AMS, SiP |
| Abstract | Use of biomedical systems, which includes healthcare systems and bio-medical implants, is increasing rapidly. These systems consist of analog and digital blocks. In order to develop these systems in short time while meeting strict size, energy and cost constraints there is need for a new design methodology. This research is focused on developing an application specific instruction-set processor (ASIP) and system in package (SiP) based common hardware platform, which could be used by different health monitoring and bio-medical systems. For fast design space exploration there a fast simulation model of complete system is also needed. Different blocks of SiP have been modeled, at different abstraction levels, using SystemC and SystemC-AMS. In this paper a sensor modeling technique, for modeling of available analog sensors, will be presented using SystemC-AMS, which will be used in the SiP simulation model. |
| PDF file |
| Title | A Cool Charger for Lithium-Ion Battery |
| Author | *Yusuke Yamamoto, Keiji Kato, Lei Lin, Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 134 - 139 |
| Keyword | Lithium-ion battery, Charger, Thermal Management |
| Abstract | Mobile systems, electric vehicle and smart house have lithium-ion battery. It has many advantages like high capacity. On the other hand, degradations of battery are occurred by various factors. We focus on thermal degradation and developed temperature management system for lithium-ion battery. This system includes inner temperature estimation system to grasp battery characteristics. We construct charging system to control temperature of battery while charging. We check about characteristic of cooling battery for charging and discharging. |
| Title | A Hardware Generator for Aesthetic Nonlinear Filter Banks |
| Author | *Tomoki Komuro, Hirotaka Nishikawa, Yukihiro Iguchi, Kaoru Arakawa (Meiji University, Japan) |
| Page | pp. 140 - 141 |
| Keyword | Signal Processing, nonlinear filter bank, aesthetic filter bank, hardware generator, FPGA |
| Abstract | This paper considers hardware realizations of nonlinear filter banks for facial beautification. First, users describe filters' characteristics and how to connect them using filter bank description languages (FDLs), then the proposed system generates Verilog HDLs to realize them.
Preliminary experimental results show that generated HDLs have the same performance as ones coded by hands. |
| PDF file |