| Title | A Heuristic Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions |
| Author | Tsutomu Sasao, *Yuta Urano, Yukihiro Iguchi (Meiji University, Japan) |
| Page | pp. 143 - 148 |
| Keyword | logic minimization, linear transform, Functional decomposition, minimul covering |
| Abstract | This paper shows a method to find a linear transformation
that reduces the number of variables to represent a given
incompletely specified index generation function.
It first generates the difference matrix, and then finds the
minimal set of variables using a covering table.
Linear transformations are used to modify the covering table
to produce a smaller solution. |
| Title | A New Design Methodology for Rounding and Hardware Minimization in Look-Up-Table-Based Arithmetic Function Evaluation |
| Author | *Shen-Fu Hsiao (National Sun Yat-sen University, Taiwan), Hou-Jen Ko (Purdue University, U.S.A.), Yu-Ling Tseng (SpringSoft, Taiwan), Chia-Sheng Wen (National Sun Yat-sen University, Taiwan) |
| Page | pp. 149 - 152 |
| Keyword | function evaluation, error analysis, truncated multiplier, digital arithmetic |
| Abstract | This paper presents a new approach of determining the bit-widths of hardware components in arithmetic function evaluators based on Look-Up Tables (LUTs) The rounding of floating-point constant values to be stored in LUTs and the hardware minimization in the subsequent arithmetic computation are considered jointly in order to optimize the entire design. The piecewise polynomial approximation with truncated multiplication is used to demonstrate the proposed method. Previous similar designs usually determine the bit widths of the quantized polynomial coefficients and the corresponding multipliers by pre-assigning allowable errors for the individual hardware components, including ROM and arithmetic units. The proposed design considers all the error sources, including the approximation errors, quantization errors, truncation errors, and final rounding errors simultaneously. Thus, the total error budget can be utilized more efficiently and the bit widths of the hardware components (ROM, multipliers, adders) can be optimized, leading to significant improvements in both area and delay. Experimental results show that the proposed method can reduce up to 48% of the total area and up to 25% of delay compared to conventional design approaches. |
| Title | A Global Router Considering Scenic Controls |
| Author | Hsueh-Ju Chou (Faraday Technology Corporation, Taiwan), Hsi-An Chien, *Ting-Chi Wang (National Tsing Hua University, Taiwan) |
| Page | pp. 153 - 158 |
| Keyword | Global Routing, Scenic Controls |
| Abstract | In this paper, we study a global routing problem that considers not
only overflow and wirelength but also scenic controls. A scenic
control is often given to a timing-critical net for coping with timing closure in a modern physical synthesis flow. We enhance an academic global router to handle scenic controls. The enhancements are (1) a new net ordering method for rip-up and reroute, (2) two length bound
allocation methods, and (3) a length-bounded adaptive multi-source
and multi-sink maze routing method. The experimental results show that
our global router is able to produce a high-quality solution in terms of overflow and wirelength without any violation of scenic controls for each test case. |
| Title | A Tuning Method of Programmable Delay Element with Two Values for Yield Improvement |
| Author | *Hayato Mashiko, Yukihide Kohira (The University of Aizu, Japan) |
| Page | pp. 159 - 164 |
| Keyword | Delay variation, Timing violation, Yield, Programmable delay element |
| Abstract | To recover the timing violations, which cause significant reduction in the yield of LSI chips, programmable delay elements called PDEs are inserted into the clock tree before fabrication and their delays are tuned after fabrication. In this paper, we use PDEs with two delay values and propose a delay tuning method of the PDE to improve the yield and to reduce the number of tests. Moreover, we evaluate the circuits obtained by the proposed method by using commercial CAD tools. |
| PDF file |
| Title | Impact of Drive Strength and Well-Contact Density on Heavy-Ion-Induced Single Event Transient |
| Author | *Jun Furuta (Kyoto University, Japan), Masaki Masuda, Katsuyuki Takeuchi, Kazutoshi Kobayashi (Kyoto Institute of Technology, Japan), Hidetoshi Onodera (Kyoto University, Japan) |
| Page | pp. 165 - 169 |
| Keyword | soft error, SET, pulse width |
| Abstract | We measure distributions of heavy-ioninduced
Single Event Transient (SET) pulse widths
from the 4 kinds of inverter chains to measure their
characteristics and estimate SET-induced soft error
rates on a Flip-Flop (FF) and a delayed TMR
FF. Measurement results show that maximum SET-induced
soft error rate on a FF is equivalent to 20%
of Single Event Upset (SEU) rate. On the delayed
TMR with 400ps delay element, SET-induced soft error
rate can be reduced by using 4x inverters with
2μm well-contact distance. |
| Title | A Technique for Accelerating Adaptive Super Resolution Technique Based on Local Features of Images Using GPU |
| Author | *Kento Kugai, Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe University, Japan) |
| Page | pp. 170 - 175 |
| Keyword | CUDA, GPGPU, Super Resolution |
| Abstract | In this paper, we propose a technique to accelerate adaptive super resolution technique based on local features of images using a Graphics Processing Unit (GPU). We have applied the acceleration technique to both super resolution process and learning process. Experimental results have shown that the proposed technique achieves speedups of 2.36 times in average, and 3.35 times at the maximum compared with the conventional technique using Central Processing Unit (CPU). |
| Title | Parallel Layer-Aware Partitioning for 3D Designs |
| Author | *Yi-Hang Chen, Yi-Ting Chen, Juinn-Dar Huang (National Chiao Tung University, Taiwan) |
| Page | pp. 176 - 179 |
| Keyword | through-silicon via, 3D integration technology, layering, partitioning, multicore architecture |
| Abstract | As compared with two-dimensional (2D) ICs, 3D integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a good solution for vertical connection, it also occupies significant silicon estate and incurs reliability problem. Because of these challenges, to minimize the number of TSVs becomes important in the design processes. Therefore, in this paper, we propose a two-phase parallel layer-aware partitioning algorithm for TSV minimization in 3D structures. In the first-phase, we employ OpenMP to parallelize the 2-way min-cut partitioning steps and get the initial solution. In the second-phase, we further improve the result by using parallel simulated annealing algorithm on GPU. The experimental results show that proposed method can reduce the number of TSVs by about 39% as compared to several existing methods. |
| PDF file |
| Title | Lithium-Ion Battery Degradation Model and Its Application to Power Management of Smart House |
| Author | *Ryosuke Miyahara, Ami Watanabe, Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 180 - 185 |
| Keyword | Smart house, battery modeling, power management |
| Abstract | Aiming at low carbon society, it is important that smart houses spread for efficient utilization of natural energy sources, e.g., photovoltaic battery. However, cost of the degradation of the batteries is a non-ignorable portion of the total cost for the power management in the smart houses. This paper discusses how to formulate the degradation of the batteries, and clarifies the efficient keys to control the cost of battery degradation. Finally, we propose an efficient power management scheme for real smart houses. |
| Title | Investigating Performance Advantages of Random Topologies on Network-on-Chip |
| Author | Sarat Yoowattana (Asian Institute of Technology, Thailand), *Ikki Fujiwara, Michihiro Koibuchi (National Institute of Informatics, Japan) |
| Page | pp. 190 - 194 |
| Keyword | Network-on-Chip, topology, interconnection networks |
| Abstract | As technology continues to scale down, the number of cores significantly increases, e.g. 64 cores.
The communication latencies increasingly give the negative impact on the performance of parallel applications on Chip MultiProcessors (CMPs). A random topology, which provides lowest diameter and average shortest path length, has been recently considered for low-latency Network-on-Chip (NoC). In this work we investigate its advantage in throughput-and-latency properties for various traffic patterns and we compare the random topology with traditional non-random topologies, such as two-dimensional mesh in various network sizes. Thorough our cycle-accurate network simulation, we found that the random topology significantly outperforms 2-D mesh and 2-D torus in terms of network latency. |
| PDF file |
| Title | Speed Traffic-Sign Recognition Algorithm for Real-Time Driving Assistant System |
| Author | *Masaharu Yamamoto, Anh-Tuan Hoang, Mutsumi Omori, Tetsushi Koide (Hiroshima University, Japan) |
| Page | pp. 195 - 200 |
| Keyword | Number recognition, Hardware implementation, Driving safety support system, Speed traffic-sign, Real-time |
| Abstract | The purpose of this research is development of an algorithm for hardware implementation for number recognition applying in speed traffic-sign recognition system for car driving assistant. We recognize the speed limit of the speed traffic-sign using hardware oriented extraction algorithm. The numbers are recognized by comparing their feature values with the recognized features. The proposed hardware oriented number recognition algorithm achieves almost 100 % in recognition rate in 31 scenes in highways and 23 scenes in local roads. |
| PDF file |
| Title | A Development and Evaluation of Variable Speed Charger System for Lithium-Ion Battery |
| Author | *Akihiro Segawa, Yusuke Yamamoto, Lei Lin, Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 201 - 202 |
| Keyword | Lithium-ion Battery, Charger, variable speed charger |
| Abstract | This paper describes a development and evaluation variable speed charger system for lithium ion battery. High speed charge is a cause to occur degradation and a safe problem because the over-current and over-voltage are supplied to the battery at charging, and temperature of the battery rises. Thus, we proposed a variable speed charge system that controls the charge current depending on the temperature rise. The variable speed charger supplies variable current during the CC (Constant Current) charge operation. That is controlling the currents to restrain a temperature rise of the battery. It reduces the damages to battery and optimally charge for a battery. |