| Title | High Speed Approximation Feature Extraction in CAD System for Colorectal Endoscopic Images with NBI Magnification |
| Author | *Tsubasa Mishima, Satoshi Shigemi, Anh-Tuan Hoang, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Rie Miyaki, Taiji Matsuo, Shigeto Yoshida, Shinji Tanaka (Hiroshima University, Japan) |
| Page | pp. 208 - 213 |
| Keyword | Dense Scale-Invariant Feature Transform (D-SIFT), Colorectal Endoscopic Images, Computer-Aided Diagnosis (CAD), Bag-of-Features (BoF), FPGA |
| Abstract | In this study, we have proposed an improvement for feature extraction in computer-aided diagnosis system for colorectal endoscopic images with narrow-band imaging (NBI) magnification. Dense Scale-Invariant Feature Transform (D-SIFT) is used in the feature extraction. It is necessary to consider a trade-off between the precision of the feature extraction and speedup by the FPGA implementation for processing of real time full high definition image. In this paper, we reduced the number of dimensions for feature representation in hardware implementation purpose. |
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| Title | An NFA-Based Programmable Regular Expression Matching Engine Highly Suitable for FPGA Implementation |
| Author | *Hiroki Takaguchi, Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City University, Japan) |
| Page | pp. 231 - 236 |
| Keyword | Regular Expression Matching, FPGA, NFA |
| Abstract | In this paper, we propose a new programmable regular expression matching engine based on a string-transition NFA. The proposed engine can perform matching at high speed, and any regular expression can be set as a pattern in a very short time. The proposed hardware engine has a two-dimensional circuit structure, and thus it is highly suitable for FPGA implementation. Comparing with an existing hardware matching engine, the effectiveness of the proposed hardware was evaluated. |
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| Title | Graphillion: ZDD-Based Software Library for Very Large Sets of Graphs |
| Author | Takeru Inoue, *Hiroaki Iwashita (Japan Science and Technology Agency, Japan), Jun Kawahara (Nara Institute of Science and Technology, Japan), Shin-ichi Minato (Hokkaido University, Japan) |
| Page | pp. 237 - 242 |
| Keyword | graph, binary decision diagram, frontier-based search, software library, Python |
| Abstract | Graphillion is a library for manipulating very large sets of graphs, based on zero-suppressed binary decision diagrams (ZDDs) with advanced graph enumeration algorithms. Graphillion is implemented as a Python extension in C++, to encourage easy development of its applications without introducing significant performance overhead. Experimental results show that Graphillion allows us to manage an astronomical number of graphs with very low development effort. |
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| Title | Clock Jitter Compensation for Continuous-Time Sigma-Delta Modulator Through Divided-by-N Feedback DAC |
| Author | *Zong-Yi Chen, Chung-Chih Hung (Department of Electrical Engineering, National Chiao Tung University, Taiwan) |
| Page | pp. 243 - 247 |
| Keyword | clock jitter, sigma-delta modulator, ADC, divided-by-n feedback DAC |
| Abstract | This paper proposes a new compensation method to overcome the high sensitivity of the continuous-time (CT) sigma-delta modulator to clock jitter by using divided-by-n (D-N) feedback DAC waveform. There are two types of clock jitter: independent clock jitter and accumulated clock jitter. This method provides a useful approach to solve one of the critical non-idealities, independent clock jitter, in the CT sigma-delta modulator without increasing the speed requirement of the modulator as well as the complexity of system and circuit design. Results prove the effectiveness of this new compensation method for independent clock jitter. |
| Title | Simultaneous Escape Routing Considering Length Matching of Differential Pairs |
| Author | Yen-Jung Lee, *Hung-Ming Chen, Ching-Yu Chin (National Chiao Tung University, Taiwan) |
| Page | pp. 248 - 252 |
| Keyword | Escape routing, differential pairs, length matching |
| Abstract | In PCB design, the escape routing problem is considered an essential part and has been widely studied in literature. There are industrial tools and some studies that work on simultaneous escape routing and escape routing of differential pairs on dense circuit boards. However, to route differential pairs simultaneously considering length-matching is still an important and on-going research problem.
In this work, inspired by prior state-of-the-arts,
we have implemented an integrated approach that achieves simultaneous escape routing considering length matching of differential pairs, our method avoids time-consuming
ILP solutions in finding length-matching differential signal paths.
Experimental results show that our approach can efficiently and effectively obtain length-matching of differential pairs on simultaneous escape routing to reduce differential-pair skews, compared with B-escape router we reimplemented. |
| Title | A Fast Trace-Driven Heterogeneous L1 Cache Configuration Simulator for Dual-Core Processors |
| Author | *Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda University, Japan) |
| Page | pp. 259 - 260 |
| Keyword | cache, simulation, multi-core |
| Abstract | Multi-core processors are used in embedded systems very often. Since
application programs running on embedded systems are much limited, there
must exists an optimal cache memory configuration in terms of speed,
power and area. Simulating application programs on various cache
configurations is one of the best options to determine the optimal
one. In this paper, we propose a very fast heterogeneous dual-core L1
cache configuration simulation method. Experimental results show that
our method runs up to 14x faster than a naive simulation algorithm. |
| Title | A Dynamic Offload Scheduler for Spatial Multitasking on Intel Xeon Phi Coprocessor |
| Author | *Takamichi Miyamoto, Kazuhisa Ishizaka, Takeo Hosomi (NEC, Japan) |
| Page | pp. 261 - 266 |
| Keyword | Intel Xeon Phi, Multi-tasking, Offload, Scheduling |
| Abstract | Intel Xeon Phi Coprocessor appears and it fully supports multitasking, but it does not automatically ensure high performance in this case. A conventional task level resource allocation scheduler could be used, but a processor utilization of the Xeon Phi is low because of idle time on the Xeon Phi. In this paper, we propose a dynamic offload scheduler which assigns processor resources of the Xeon Phi to tasks by an offload level. We describe an effectiveness of the proposed method with evaluations. |
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| Title | A Restricted Dynamically Reconfigurable Architecture for Low Power Processors |
| Author | *Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido University, Japan) |
| Page | pp. 267 - 268 |
| Keyword | Reconfigurable system, Processor architecture, Embedded system |
| Abstract | In this paper, we propose a Control-flow Driven Data-flow Switching variable datapath architecture for embedded applications that demand extremely low power consumption and a wide range of usage.
In the proposed architecture aim to achieve both flexibility and low power consumption by limiting the scope of dynamic reconfiguration.
As a preliminary evaluation, we have mapped a small program to understand the fundamental characteristics of the proposed architecture. |
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| Title | A Processor Architecture for Motion Sensing Systems Using Accelerometer |
| Author | *Takashi Matsuo, Arif Ullah Khan (Graduate School of Information Science and Technology, Osaka University, Japan), Takashi Hamabe (MICRONIX Inc., Japan), Yoshinori Takeuchi, Masaharu Imai (Graduate School of Information Science and Technology, Osaka University, Japan) |
| Page | pp. 269 - 274 |
| Keyword | ASIP, Coordinate transform, Power consumption, Accelerometer, Motion sensing |
| Abstract | Microelectromechanical-systems-based accelerometers are widely used in motion sensing, in which coordinate system transform is the major process. In this study, a method for coordinate system transform is introduced, and a low-power processor architecture specialized for coordinate system transform is proposed and evaluated. Through experimental results, the proposed processor reduced energy consumption by 48.3% compared with a conventional RISC processor implementation. |
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| Title | Event Modeling Method for Verification of Power Analysis Attacks |
| Author | *Kyota Sugioka, Toshiya Asai, Masaya Yoshikawa (Meijo University, Japan) |
| Page | pp. 280 - 281 |
| Keyword | Tamper resistance, power analysis attacks, cryptographic circuit |
| Abstract | To evaluate the resistance of a cryptographic circuit to power analysis attacks during the design stage, this paper proposes a method to improve the efficiency of the acquisition process of information about power consumption, which requires a large number of encryption simulations. The proposed method newly introduces an event modeling method, maintains accuracy equivalent to that of a simulation program with an integrated circuit emphasis (SPICE), and acquires information about power consumption within a realistic processing timeframe that is similar to that of a logic simulation. |
| Title | A Variable-Length String Matching Circuit Based On SeqBDDs |
| Author | *Atsushi Matsuo, Yasunori Takagi (Ritsumeikan University, Japan), Hiroki Nakahara (Kagoshima University, Japan), Shigeru Yamashita (Ritsumeikan University, Japan) |
| Page | pp. 282 - 287 |
| Keyword | String Matching, Haradware, Programmable Sequence Logic, Sequence Binary Decision Diagram |
| Abstract | This paper proposes a new hardware
architecture for fast string matching. The proposed
method utilizes a concept of Sequence Binary Decision
Diagrams that is an efficient data structure to
store a set of string sequences. Our proposed architecture
is a natural extension of an Programmable Sequence
Logic Circuit to SeqBDDs. The naive implementation
of the Programmable Sequence Logic takes
one character in one clock cycle, and thus we seek a
way to evaluate multiple characters in one clock cycle
with some Content-addressable memories (CAMs).
We also report preliminary evaluations for the proposed
architectures. |
| Title | An Image Compression Method for Frame Memory Size Reduction Using Local Feature of Images |
| Author | *Yuki Fukuhara (Osaka University, Japan), Akihisa Yamada (Sharp Corporation/Osaka University, Japan), Takao Onoye (Osaka University, Japan) |
| Page | pp. 288 - 289 |
| Keyword | frame memory, image compression, system architecture |
| Abstract | This paper proposes a method of image compression aiming at reduction of frame memory size of digital appliances. In spite of adopting a variable length coding, this method can guarantee the minimum compression ratio by adaptively controlling pixel data reduction rate. Utilizing local feature of images, the reduction rate is more finely controlled so as to maintain visual quality of images. Experimental results show that it attains a compression ratio of 1/3, while keeping visual quality of images by means of adequate bit allocation. |
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