| Title | A Study of ESD Clamp Placement Impact on Peripheral- and Area-I/O Designs |
| Author | *Yi-Cheng Liang, Hung-Ming Chen, Ming-Fang Lai (National Chiao Tung Univ., Taiwan) |
| Page | pp. 292 - 297 |
| Detailed information (abstract, keywords, etc) | |
| Title | Customizable Hardware Architecture of Support Vector Machine in CAD System for Colorectal Endoscopic Images with NBI Magnification |
| Author | *Satoshi Shigemi, Tsubasa Mishima, Anh-Tuan Hoang, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Rie Miyaki, Taiji Matsuo, Shigeto Yoshida, Shinji Tanaka (Hiroshima Univ., Japan) |
| Page | pp. 298 - 303 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | Analysis of Corner Conditions in PVT Variations and Reliability Degradations |
| Author | Atsushi Kurokawa, *Masayuki Watanabe, Makoto Hoshi, Tetsuya Kobayashi, Masa-aki Fukase (Hirosaki Univ., Japan) |
| Page | pp. 304 - 309 |
| Detailed information (abstract, keywords, etc) | |
| Title | High Level Synthesis with Stream Query to C Parser: Eliminating Hardware Development Difficulties for Software Developers |
| Author | *Eric Shun Fukuda (Hokkaido Univ., Japan), Takashi Takenaka, Hiroaki Inoue (NEC, Japan), Hideyuki Kawashima (Univ. of Tsukuba, Japan), Tetsuya Asai, Masato Motomura (Hokkaido Univ., Japan) |
| Page | pp. 310 - 315 |
| Detailed information (abstract, keywords, etc) | |
| Title | Faster Multiple Pattern Matching System on GPU Based on Bit-Parallelism |
| Author | *Hirohito Sasakawa, Hiroki Arimura (Hokkaido Univ., Japan) |
| Page | pp. 316 - 321 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | High-Level Synthesis for Nested Loop Kernels with Non-Uniform Dependencies |
| Author | *Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ., Japan) |
| Page | pp. 322 - 327 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | A Fast Simplification Algorithm for Packet Classification |
| Author | *Infall Syafalni (Kyushu Inst. of Tech., Japan), Tsutomu Sasao (Meiji Univ., Japan) |
| Page | pp. 328 - 333 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Low Energy Full TMR Design Method with Optimized Selection of Time/Space TMR Mode and Supply Voltage |
| Author | *Kazuhito Ito, Yuki Hayashi (Saitama Univ., Japan) |
| Page | pp. 334 - 339 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | Via-Configurable Structured Asic Using Dual Supply Voltages |
| Author | Ta-Kai Lin (Yuan Ze Univ., Taiwan), Kuen-Wey Lin (National Chiao Tung Univ., Taiwan), Chang-Hao Chiu, *Rung-Bin Lin (Yuan Ze Univ., Taiwan) |
| Page | pp. 340 - 341 |
| Detailed information (abstract, keywords, etc) | |
| Title | Automatic On-Chip Interface Synthesis Between Incompatible Protocols with Advanced Features |
| Author | *Jiayi Zhang, Masahiro Fujita (Univ. of Tokyo, Japan) |
| Page | pp. 342 - 347 |
| Detailed information (abstract, keywords, etc) | |
| Title | Low-Power Op-Amp with Capacitor-Base On-Chip Power Supply |
| Author | *Kazuhiro Hanada, Shigetoshi Nakatake (Univ. of Kitakyushu, Japan) |
| Page | pp. 348 - 353 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | A Basic-Block Level Optimistic Energy Estimation for Power-Gated VLIW Data-Path Model |
| Author | *Shunsuke Nakamura, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ., Japan) |
| Page | pp. 354 - 359 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Memory-Saving Technique for 4K Super-Resolution Circuit with Binary Tree Dictionary |
| Author | *Ayumi Kiriyama, Ryo Matsuzuka, Kohei Michibata, Takahiro Kitayama, Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
| Page | pp. 360 - 365 |
| Detailed information (abstract, keywords, etc) | |
| Title | HLS Utilizing Area Optimizing Method for High-Definition MRA-TV Denoise Circuit |
| Author | *Eita Kobayashi, Kenta Senzaki, Atsufumi Shibayama, Yuichi Nakamura (NEC, Japan) |
| Page | pp. 366 - 371 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | A Circuit Design Method for Dynamic Reconfigurable Circuits |
| Author | *Hajime Sawano, Takashi Kambe (Kinki Univ., Japan) |
| Page | pp. 372 - 376 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | Concurrent Verification Experience of Cache Protocol in Real Development of Large SMP Server Product by Using Model Checking |
| Author | *Toru Shonai (Hitachi, Japan), Shoichi Hanaki (OKANO Electric, Japan), Yoshiaki Kinoshita (Hitachi, Japan) |
| Page | pp. 377 - 382 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | Implementation of Strictly Convex QP Solver with Multiple Precision Arithmetic |
| Author | *Masahiro Kimura, Hiroshige Dan (Kansai Univ., Japan) |
| Page | pp. 383 - 386 |
| Detailed information (abstract, keywords, etc) | |