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SASIMI 2015
The 19th Workshop on Synthesis And System Integration of Mixed Information Technologies

Poster II
Time: 16:10 - 17:55 Monday, March 16, 2015
Chairs: Eita Kobayashi (NEC, Japan), Chun-Yao Wang (National Tsing Hua Univ., Taiwan)

R2-1 (Time: 16:10 - 16:12)
TitleFast Transient and High Current Efficiency Voltage Regulator with Hybrid Dynamic Biasing Technique
AuthorChia-Min Chen, *Yen-Wei Liu, Chung-Chih Hung (National Chiao Tung Univ., Taiwan)
Pagepp. 119 - 122
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R2-2 (Time: 16:12 - 16:14)
TitleA BIST Scheme Detecting Catastrophic Faults of MOSFETs in Bandgap Reference with Self-Biased Operational Amplifier
Author*Takuya Bando, Masayoshi Tachibana (Kochi Univ. of Tech., Japan)
Pagepp. 123 - 127
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R2-3 (Time: 16:14 - 16:16)
TitleScan Test of Latch-Based Asynchronous Pipeline Circuits under 2-Phase Handshaking Protocol
Author*Kyohei Terayama, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ., Japan)
Pagepp. 128 - 133
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R2-4 (Time: 16:16 - 16:18)
TitleData Reduction and Parallelization for Human Detection System
Author*Mao Hatto, Takaaki Miyajima, Hideharu Amano (Keio Univ., Japan)
Pagepp. 134 - 139
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R2-5 (Time: 16:18 - 16:20)
TitleEvaluation of Approximate SAD Circuits with Error Compensation
Author*Toshihiro Goto, Yasunori Takagi, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Pagepp. 140 - 145
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R2-6 (Time: 16:20 - 16:22)
TitleA Circuit Implementable 5-Output nMOSFET Shearing Stress Sensor
Author*Tomochika Harada, Kousuke Takeuchi (Yamagata Univ., Japan)
Pagepp. 146 - 148
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R2-7 (Time: 16:22 - 16:24)
TitleIddq Testing Against Process Variations and Measurement Noises
AuthorChia-Ling Chang, *Jack Sheng-Yan Lin, Clarles Hung-Pin Wen (National Chiao Tung Univ., Taiwan)
Pagepp. 149 - 150
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R2-8 (Time: 16:24 - 16:26)
TitlePre-Bond Interposer Test Methodology for System in Package
AuthorKatherine Shu-Min Li (National Sun Yat-sen Univ., Taiwan), Sying-Jyan Wang (National Chung Hsing Univ., Taiwan), Cheng-You Ho (National Sun Yat-sen Univ., Taiwan), Yingchieh Ho (National Dong Hwa Univ., Taiwan), Ruei-Ting Gu (National Sun Yat-sen Univ./Advanced Semiconductor Engineering (ASE) Group, Taiwan), Bo-Chuan Cheng (Advanced Semiconductor Engineering (ASE) Group, Taiwan)
Pagepp. 151 - 156
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R2-9 (Time: 16:26 - 16:28)
TitleOxygen Sensor Module with Majority Sensing for Monitoring Wide Area at Disaster
Author*Ryuta Nishino, Tatsuya Yamada, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)
Pagepp. 157 - 158
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R2-10 (Time: 16:28 - 16:30)
TitleFPGA Implementation and Evaluation of Image Scaling Circuits Using Seletor-Logic-Based Bi-Linear Interpolation
Author*Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ., Japan)
Pagepp. 159 - 160
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R2-11 (Time: 16:30 - 16:32)
TitleAn Accelerator for Frequent Itemset Mining from Data Stream with Parallel Item Tree
Author*Kasho Yamamoto, Tsunaki Sadahisa, Dahoo Kim, Eric S. Fukuda, Tetsuya Asai, Masato Motomura (Hokkaido Univ., Japan)
Pagepp. 161 - 162
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R2-12 (Time: 16:32 - 16:34)
TitleA Leakage Current Reduction Algorithm Using Input Vector Control and Cell Topology Modification
AuthorTsung-Yi Wu (National Changhua Univ. of Education, Taiwan), Hsin-Hui Li (Global Unichip, Taiwan), *Zhi-Yao Ding, Guan-Cheng Guo (National Changhua Univ. of Education, Taiwan)
Pagepp. 163 - 164
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R2-13 (Time: 16:34 - 16:36)
TitleMajority-Inverter Graph for FPGA Synthesis
Author*Luca Amaru (EPFL - LSI, Switzerland), Ana Petkovska (EPFL - LAP, Switzerland), Pierre-Emmanuel Gaillardon (EPFL - LSI, Switzerland), David Novo Bruna, Paolo Ienne (EPFL - LAP, Switzerland), Giovanni De Micheli (EPFL - LSI, Switzerland)
Pagepp. 165 - 170
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R2-14 (Time: 16:36 - 16:38)
TitleHigh Observability Scan Chains with Improving Output Compaction Efficiency
AuthorSying-Jyan Wang, Che-Wei Kao (National Chung Hsing Univ., Taiwan), Katherine Shu-Min Li (National Sun Yat-sen Univ., Taiwan)
Pagepp. 171 - 176
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R2-15 (Time: 16:38 - 16:40)
TitleUsing Structural Relations for Checking Combinationality of Cyclic Circuits
AuthorWan-Chen Weng (National Tsing Hua Univ., Taiwan), Yung-Chih Chen (Yuan Ze Univ., Taiwan), Jui-Hung Chen, *Ching-Yi Huang, Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Pagepp. 177 - 182
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R2-16 (Time: 16:40 - 16:42)
TitleYAPSIM: Yet Another Parallel Logic Simulation Using GP-GPU
Author*Takuya Hashiguchi, Yuichiro Mori, Masahiko Toyonaga, Michiaki Muraoka (Kochi Univ., Japan)
Pagepp. 183 - 186
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R2-17 (Time: 16:42 - 16:44)
TitleTechnology Mapping Method for Low Power Consumption and High Performance in General-Synchronous Framework
Author*Junki Kawaguchi, Yukihide Kohira (Univ. of Aizu, Japan)
Pagepp. 187 - 192
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R2-18 (Time: 16:44 - 16:46)
TitleA Quaternary Master-Slave Flip-Flop with Multiple Functions for Multi-Valued Logics
Author*Renyuan Zhang, Mineo Kaneko (JAIST, Japan)
Pagepp. 193 - 198
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R2-19 (Time: 16:46 - 16:48)
TitleQuantitative Evaluations and Efficient Exploration for Optimal Partially-Programmable Circuits Generation
Author*Takumi Tsuzuki (NAIST, Japan), Yuko Hara-Azumi (Tokyo Inst. of Tech., Japan), Shigeru Yamashita (Ritsumeikan Univ., Japan), Yasuhiko Nakashima (NAIST, Japan)
Pagepp. 199 - 204
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R2-20 (Time: 16:48 - 16:50)
TitleA Variability-Aware Energy-Efficient On-Chip Memory for Near-Threshold Operation Using Cell-Based Structure
Author*Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ., Japan)
Pagepp. 205 - 210
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R2-21 (Time: 16:50 - 16:52)
TitleAn Efficient Calculation Method for Reliability Analysis of Logic Circuits
Author*Masatoshi Tsushima, Yuichi Ikeda, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Pagepp. 211 - 216
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