| Title | New nMOS Dynamic Shift Registers for Driver Circuit of Small LCDs and Their Evaluations |
| Author | *Shinji Higa, Shuji Tsukiyama (Chuo University, Japan), Isao Shirakawa (University of Hyogo, Japan) |
| Page | pp. 218 - 223 |
| Keyword | shift register, nMOS dynamic logic, Liquid Crystal Display, System on Glass, source driver |
| Abstract | Driver circuits for small LCDs (Liquid Crystal Displays) are formed on the same glass substrate as LCD by means of thin film transistors, which is called system on glass technology. If such a driver circuit is implemented by nMOS transistor only, then production cost can be reduced, because pMOS process is eliminated. In this paper, we focus on shift registers, which are indispensable in LCD driver circuit, and consider a method to design an nMOS dynamic shift register. Then, we propose two new 2-phase clock shift registers, and evaluate their performances by comparing them with the conventional shift registers using 2-phase or 4-phase clock. The results show that the new shift registers have acceptable areas and outperform the others in speed, power, and variations of power supply voltage and mobility of transistors. |
| Title | A Floorplan-Driven High-Level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs |
| Author | *Koichi Fujiwara, Masao Yanagisawa, Nozomu Togawa (Waseda University, Japan) |
| Page | pp. 224 - 225 |
| Keyword | high-level synthesis (HLS), FPGA, floorplan, interconnection delay |
| Abstract | Recently, high-level synthesis (HLS) techniques for FPGA designs are required such as in image processing and software-defined radios. With recent process scaling in FPGAs, interconnection delays become dominant in total circuit delays and each FPGA family has different interconnection delay characteristics. Multiplexer cost is another concern in FPGA designs. We need to consider interconnection delays based on interconnection delay characteristics in FPGA designs with reducing multiplexer cost in HLS. In this paper, we propose a floorplan-driven HLS algorithm utilizing interconnection delay characteristics in FPGA designs. Experimental results show that our algorithm can realize FPGA designs which reduce the latency by up to 6% compared with our previous approach. |
| Title | Introducing Loop Statements in Random Testing of C Compilers Based on Expected Value Calculation |
| Author | *Kazuhiro Nakamura, Nagisa Ishiura (Kwansei Gakuin University, Japan) |
| Page | pp. 226 - 227 |
| Keyword | compiler, random testing, for loop |
| Abstract | This paper presents a method of reinforcing random testing of C compilers by introducing loop statements.
While random testing based on precomputation of expected values is powerful in detecting bugs in C compilers, loop statements have not been handled, due to difficulties in avoiding undefined behavior.
In this paper, an extended method to eliminate undefined behavior in loop bodies is proposed, where arrays of precomputed constants are used to modify problematic operands during loop iterations.
A random test system based on the proposed method has uncovered a new bug in the latest version of LLVM which can not be detected by the existing methods. |
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| Title | Product Term Minimization in ROBDDs with Application to Reconfigurable SET Array Synthesis |
| Author | *Yi-Hang Chen, Yang Chen, Juinn-Dar Huang (National Chiao Tung University, Taiwan) |
| Page | pp. 228 - 231 |
| Keyword | single-electron transistor, automatic synthesis, reconfigurable, area minimization, binary decision diagram |
| Abstract | The power dissipation has become a crucial issue for most electronic circuit and system designs nowadays when fabrication processes exploit even deeper submicron technology. In particular, leakage power is becoming a dominant source of power consumption. In recent years, the reconfigurable single-electron transistor (SET) array has been proposed as an emerging circuit design style for continuing Moore’s Law due to its ultra-low power consumption. Several automated synthesis techniques for area minimization have been developed for the reconfigurable SET array in the past few years. Nevertheless, most of those existing methods focus on variable and product term reordering during SET mapping. In fact, minimizing the number of product terms can greatly reduce the area as well, which has not been well addressed before. In this paper, we propose a dynamic shifting based variable ordering algorithm that can minimize the number of disjoint sum-of-product terms extracted from the given ROBDD. Experimental results show that the proposed method can achieve an area reduction of up to 49% as compared to current state-of-the-art techniques. |
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| Title | An Effective Timing-Coherent Transactor Generation Approach for Mixed-Level System Simulations |
| Author | *Hsin-I Wu, Li-chun Chen, Ren-Song Tsay (National Tsing Hua University, Taiwan) |
| Page | pp. 232 - 237 |
| Keyword | Mixed-level simulations, system simulations, transactor, timing coherent, ESL |
| Abstract | In this paper we extend the concept of the traditional transactor, which focuses on correct content transfer, to a new timing-coherent transactor that also accurately aligns the timing of each transaction boundary so that designers can perform precise concurrent system behavior analysis in mixed-abstraction-level system simulations which are essential to increasingly complex system designs. To streamline the process, we also developed an automatic approach for timing-coherent transactor generation. Our approach is actually applied in mixed-level simulations and the results show that it achieves 100% timing accuracy while the conventional approach produces results of 25% to 44% error rate. |
| Title | An Accurate Processor Power Estimation Approach Based on Microcomponent Structure Analysis |
| Author | *Chi-Kang Chen, Zih-Ci Huang, Ren-Song Tsay (National Tsing Hua University, Taiwan) |
| Page | pp. 238 - 243 |
| Keyword | ESL, power estimation, microcomponent, power anslysis, processor |
| Abstract | We propose a new embedded processor power analysis approach that maps instruction executions to microarchitecture components for highly efficient and accurate power evaluations, which are crucial for embedded system designs. We observe that in practice, the execution of each high-level instruction in a processor always triggers the same microcomponent activity sequence while the difference of power consumption values of different instructions is mainly due to timing variations caused by hazards and cache misses. Hence, by incorporating accurately pre-characterized microcomponent power consumption values into an efficient instruction-microcomponent processor timing simulation tool, we construct a highly accurate embedded processor power analysis tool. Additionally, based on the proposed approach, we accurately and effortlessly capture the power waveform at any time point for power profiling, peak power and dynamic thermal distribution analysis. The experimental results show that the proposed approach is nearly as accurate as gate-level simulators, with an error rate of less than 1.2% while achieving simulation speeds of up to 20 MIPS, five orders faster than a commercial gate-level simulator. |
| Title | A Verilog Compiler Proposal for VerCPU Simulator |
| Author | *Tze Sin Tan (Altera Corporation, Malaysia), Bakhtiar Affendi Rosdi (Universiti Sains Malaysia, Malaysia) |
| Page | pp. 244 - 249 |
| Keyword | Verilog, Simulator, Hardware Assisted |
| Abstract | Verilog is a widely used Hardware Description Language (HDL) for VLSI design and modeling. As a language developed with hardware execution concurrency in mind, Verilog can be mapped onto a dedicated processor for higher simulation throughput. The processor requires a compiler to transform Verilog netlist into compiled-code instructions. In this paper, we propose a data structure that adequately
represents a Verilog model. Then, the Verilog compiler is developed to map Verilog netlist into this data structure. We also demonstrated that it is possible to construct a hardware simulator (VerCPU) utilizing this data structure. |
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| Title | MorFPGA Duo: A Dual-Core FPGA-Based Embedded System Development Platform |
| Author | Chih-Chyau Yang, *Chun-Yu Chen, Chun-Wen Cheng, Yi-Jun Liu, Chien-Ming Wu, Chun-Ming Huang (National Chip Implementation Center, Taiwan) |
| Page | pp. 250 - 254 |
| Keyword | MorFPGA, MorFPGA Duo, SoC FPGA, All-programmable SoC |
| Abstract | To help academia researchers of Taiwan rapidly integrate their IP to a system for complete demonstration of hardware/software co-design, CIC presents a platform named MorFPGA Duo in this paper. MorFPGA Duo owns a dual core, versatile built-in peripherals and high expandability to satisfy users’ eager needs for state-of-the-art research topics. MorFPGA Duo consists of two boards: The core modular board mainly includes a dual core Zynq and versatile peripherals while the multimedia modular board supports the high quality two-channel video sources with SDI interface. With the PMOD and FMC connectors, the various kinds of daughter boards are enabled to integrate into MorFPGA Duo system. The Media Wiki online forum is adopted as the platform to deliver users the latest lab materials. The design flow and two system integration examples are provided to show the MorFPGA Duo is workable. One example introduces how the software and hardware design can be integrated and demonstrated in this platform. The other example shows the video demo system with dual SDI cameras to enable the future development of 3D video applications. |
| Title | A 3G-Based Bridge Structural Health Monitoring System Using Cost-Effective 1-Axis Accelerometers |
| Author | Chih-Hsing Lin, *Wen-Ching Chen, Chih-Ting Kuo, Gang-Neng Sung, Chih-Chyau Yang, Chien-Ming Wu, Chun-Ming Huang (National Chip Implementation Center, Taiwan) |
| Page | pp. 255 - 259 |
| Keyword | Bridge health monitoring, 1-axis accelerometer, Cellular communication |
| Abstract | This paper proposes a 3G-based structure health
monitoring device (HMD) for short-term monitoring. The
proposed HMD includes three 1-axis accelerometers, microcontroller unit (MCU), analog to digital converter (ADC), and
cellular gateway for long span bridge. The proposed monitoring
system achieves the features of low cost by using three 1-axis
accelerometers with the data synchronization problem being
solved, and easily installation and removal. Furthermore, instead
of using data loggers data is transmitted to Host through 3G
gateway. Compared with 3-axis accelerometer, our proposed
1-axis accelerometers based device has achieved 72.7% cost
saving. Besides, the cost of HMD achieves 34.1% cost saving
when it is compared with data logger inside HMD. To adapt
our HMD system to fit different monitoring environments, the
proposed system can easily exchange the different PCB boards
to achieve variety applications such as communication interfaces
and sensors. Therefore, with using the proposed device, the realtime diagnosis system for bridge damage monitoring can be
conducted effectively. |
| Title | Protection Method for AES IP Core from Scan-Based Attack |
| Author | *Yifan Wu, Shinji Kimura (Waseda University, Japan) |
| Page | pp. 266 - 271 |
| Keyword | Advanced Encryption Standard, scan chain, secure scan design, bit difference attack, JTAG |
| Abstract | In the research, scan-based two bit difference attack method has been studied and complete the method by further analysis and additional tables and test patterns. Then a protection method for such scan-based attack is also proposed.The proposed method cause less area overhead compared with the original AES IP core, higher security level and fault coverage compared to previous methods. |
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| Title | Using Range-Equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking |
| Author | Yung-Chih Chen (Yuan Ze University, Taiwan), Wei-An Ji, Chih-Chung Wang, *Ching-Yi Huang, Chun-Yao Wang (National Tsing Hua University, Taiwan) |
| Page | pp. 278 - 282 |
| Keyword | design verification, bounded sequential equivalence checking |
| Abstract | This paper presents a method based on range-equivalent circuit technique for SAT-based bounded sequential equivalence checking. Given two sequential circuits to be verified, instead of straightforward unrolling the miter of two sequential circuits, we iteratively minimize the miter with a range-equivalent circuit technique before adding a new timeframe. This is because the previous timeframes can be considered as a pattern generator that feeds input patterns to the next timeframe. Experimental results show that the proposed method saved up to 91% of time for reaching the same bounded depth compared with previous work on IWLS2005 benchmarks. |
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| Title | A Redundant Task Allocation Method for Reliable Network-on-Chips |
| Author | *Hiroshi Saito (The University of Aizu, Japan), Tomohiro Yoneda (National Institute of Informatics, Japan), Yuichi Nakamura (NEC, Japan) |
| Page | pp. 287 - 292 |
| Keyword | network-on-chips, task allocation, task scheduling, fault tolerance |
| Abstract | The possibility of failures on network-on-chip (NoC) will be increased if the size increases. To realize reliable NoCs, we propose a redundant task allocation method which allocates several copies of tasks to different cores based on multiple task scheduling. In the experiments, we apply the proposed method to a real application. Then, the allocation
time of the proposed method and the estimated execution time of the application are evaluated changing parameters such as multiplicities of scheduling and allocation. |
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| Title | A Cooling Effect Formulation and Implementation of a Cooling System for Li-Ion Battery Modules |
| Author | *Yuki Kitagawa, Yusuke Yamamoto, Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 305 - 310 |
| Keyword | Lithium-ion battery, Degradation, Air cooling |
| Abstract | This paper discusses the theory and experiments of heating and air cooling of battery modules. Heating mechanism is shown first, and cooling of a single battery is examined. Optimum air flow speed is discussed. Then, similar discussion is made for a battery module of six serial cells. Finally, the discussion is to reduce the temperature variation |
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| Title | Global Transformation-Based Optimization of Threshold Logic Circuits |
| Author | *Maiko Kabu, Takayuki Kasugai, Shigeru Yamashita (Ritsumeikan University, Japan), Chun-Yao Wang (National Tsing Hua University, Taiwan) |
| Page | pp. 311 - 316 |
| Keyword | optimization, threshold logic circuit, global functional flexibility, CSPF |
| Abstract | Threshold logic circuit technology, which is considered to be one of the promising new technologies, has been successfully demonstrated recently thanks to the rapid progress of nanotechnology. Since the logic elements used in threshold logic circuits are very different from the ones used in the conventional logic circuits, we may need a totally different design methodology for threshold logic circuits; there have been intensive studies recently. In such previous works, local transformation have been mainly considered for the optimization of circuits. Instead, this paper, for the first time, considers global transformations. More specifically, we propose a method to calculate global functional flexibility based on compatible sets of permissible functions (CSPFs) and how to use it to optimize threshold logic circuits. |
| Title | An ECO-Friendly Design Style Based on Reconfigurable Cells |
| Author | *Yudai Kabata, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe University, Japan) |
| Page | pp. 319 - 324 |
| Keyword | ECO, reconfigurable cell, error diagnosis, technology remapping |
| Abstract | This paper presents an ECO-friendly design style based on reconfigurable (RECON) cells to reduce an increase in circuit delay by post-mask Engineering Change Orders (ECO’s). Employing RECON cells to implement not only the changes caused by ECO’s but also a part of the original circuit is the key to provide higher flexibility in the ECO process. Experimental results have shown that the proposed design style is effective to reduce the increase in circuit delay with post-mask ECO. |