| Title | Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults - from Device to Circuit Level |
| Author | Hsuan-Ming Huang, *Yi-Wu Liu, Charles H.-P. Wen (National Chiao Tung University, Taiwan) |
| Page | pp. 327 - 332 |
| Keyword | Soft error, Multiple transient fault, Reliability |
| Abstract | Considering the structure of the layout and resulting nuclear reactions, multiple transient faults tend to be induced more frequently than do single transient faults, due to the effects of technology scaling. This study proposes a layout-based soft error estimation framework, which takes into account multiple transient faults from the device level to the circuit level. Experiment results demonstrate that the soft error rate can be underestimated by an average of 15.72% if only single (rather than multiple) transient faults are taken into account. Our results indicate that netlist-based analysis for the estimation of soft error rates is no longer sufficient, due to the overwhelming influence of the structural layout. Thus, using benchmark c432, a tighter layout will result in a soft error rate 34% higher than that generated in a looser layout. |
| Title | Using Body Biasing for Energy Efficient Frequency Scaling in a Dynamically Reconfigurable Processor |
| Author | *Johannes Maximilian Kühn (University of Tübingen, Germany), Hideharu Amano (Keio University, Japan), Wolfgang Rosenstiel (University of Tübingen, Germany) |
| Page | pp. 333 - 338 |
| Keyword | Body Biasing, SOI, DVFS |
| Abstract | STMicro’s 28nm UTBB-FDSOI process is examined regarding the interplay of voltage and frequency scaling and coarse-grained body biasing in a Dynamically Reconfigurable Processor. We show that through coarse-grained body biasing, 37.79% and 40.76% greater energy efficiency at supply voltages of 0.6V and 0.8V are attainable compared to scaling supply voltages. Coarse-grained body biasing further optimizes energy efficiency by 16.1%, 10.6% and 12.8% at 0.6V, 0.8V and 1.0V over whole chip body biasing. No architectural changes are required. |
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| Title | Low-Power Gated Clock Tree Synthesis for 3D ICs |
| Author | *Yu-Chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin (National Chung Cheng University, Taiwan) |
| Page | pp. 339 - 343 |
| Keyword | clock tree, clock gating, 3D IC |
| Abstract | Applying clock gating in three dimensional integrated circuits (3D ICs) is essential for reducing power con- sumption and improving circuit reliability. However, the previous works only present algorithms for 3D clock tree synthesis. None of them address gated clock tree in 3D ICs for dynamic power reduction. In this paper, we propose the first problem formulation in the literature for 3D gated clock network optimization. We apply multilevel framework to effectively construct the topological gated clock tree while considering flip-flop switching activities and the timing constraint of enable signal paths at clock gating cells. Based on the constructed topological gated clock tree, a zero-skew 3D clock routing tree is then generated. Experimental results show that, compared with conventional 3D clock tree synthesis, the proposed 3D gated clock tree synthesis can achieve much less power consumption with similar number of TSVs and clock tree wirelength. |
| Title | Graph-Covering-Based Architectural Synthesis for Programmable Digital Microfluidic Biochips |
| Author | *Daiki Kitagawa, Dieu Quang Nguyen, Trung Anh Dinh, Shigeru Yamashita (Ritsumeikan University, Japan) |
| Page | pp. 344 - 349 |
| Keyword | graph, binding, scheduling, programmable, biochip |
| Abstract | Digital microfluidic technology has been extensively applied in various biomedical fields. Different from application-specific biochips, a programmable design has several advantages such as dynamic reconfigurability and general applicability. Basically, a programmable biochip divides the chip into several virtual modules. However, in the previous design, a virtual module can execute only one operation at a time. In this paper, we propose a new multi-functional module for programmable digital microfluidic biochips, which can execute two operations simultaneously. Moreover, we also propose a binding and scheduling algorithm for programmable biochips, which is motivated from a graph-covering problem. Experiment demonstrates that our algorithm can reduce the completion time of the applications compared with the previous approaches. |
| Title | Contamination-Aware Routing Flow for Both Functional and Washing Droplets in Digital Microfluidic Biochips |
| Author | *Qin Wang, Yiren Shen, Hailong Yao (Tsinghua University, China), Tsung-Yi Ho (National Chiao Tung University, Taiwan), Yici Cai (Tsinghua University, China) |
| Page | pp. 350 - 355 |
| Keyword | Contamination-Aware Routing, Washing Droplets Routing, Digital Microfluidic Biochips |
| Abstract | A major issue in digital microfluidic biochips is cross-contamination caused by different biomolecule droplets crossing the same sites, where washing operations are necessary to avoid wrong assay results. Existing works either assume unrealistic infinite washing capacity, or ignore execution-time constraint and/or routing conflicts between functional and washing droplets. This paper presents the first practical droplet routing flow considering both realistic washing capacity constraint and routing conflicts between washing and functional droplets. Experimental results are promising. |
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| Title | Obstacle-Avoiding Wind Turbine Placement for Power-Loss and Wake-Effect Optimization |
| Author | *Yu-Wei Wu (National Cheng Kung University, Taiwan), Yi-Yu Shi (Missouri University of Science and Technology, U.S.A.), Sudip Roy (National Cheng Kung University, Taiwan), Tsung-Yi Ho (National Chiao Tung University, Taiwan) |
| Page | pp. 356 - 361 |
| Keyword | Placement, Wind Turbine |
| Abstract | As finite energy resources are being consumed at fast rate than they can be replaced, renewable energy resources have drawn an extensive attention. Wind power development is one such example, which is growing significantly throughout the world. The main difficulty in wind power development is that wind turbines interfere with each other and such turbulent directly affects the power produced, known as the wake effect. In addition, wirelength among wind turbines is not merely an economic factor, but also more decides the power loss occurs in the wirelength. Moreover, in reality, obstacles exist in the wind farm which is unavoidable, e.g., private land, lake. Nevertheless, to the best of our knowledge, none of the existing works consider wake effect, wirelength and obstacle-avoiding at the same time in the wind turbine placement problem. In this paper, we propose an analytical method to solve obstacle-avoiding placement of wind turbines for power-loss and wake-effect optimization. Experimental results show that the wind power produced by our tool is similar to that by the industrial tool AWS OpenWind. Besides, our algorithm can reduce the wirelength and avoid obstacles successfully while finding the locations of wind turbines at the same time. |
| Title | Accelerating Random-Walk-Based Power Grid Analysis through Error Smoothing |
| Author | *Tsuyoshi Okazaki, Masayuki Hiromoto, Takashi Sato (Kyoto University, Japan) |
| Page | pp. 362 - 367 |
| Keyword | power grid analysis, random walk, Gauss-Seidel method |
| Abstract | This paper proposes a hybrid solver of a random walk and a stationary iterative method. Our solver is based on quasi-zero-variance importance sampling (QZV-IS), in which walk-probability is updated by using coarsely estimated voltages for rapid convergence. Because the convergence speed depends on the smoothness of the estimated voltages, we propose additionally to apply smoothing operator to quickly improve the quality of the estimated voltages. The propose solver achieved 2.3-3.6x speedup compared to the conventional method that only utilizes QZV-IS. |
| Title | Improvement of Simulated Annealing Search ---Based on Tree Representations--- |
| Author | *Takaaki Banno, Kunihiro Fujiyoshi (Tokyo University of Agriculture and Technology, Japan) |
| Page | pp. 368 - 373 |
| Keyword | Simulated Annealing, tree representations, O-tree, DTS, packing |
| Abstract | Placement problem for LSI layout is often refered to ``Rectangle packing problem.'' For this problem, several representations of rectangle packing were proposed and packings are searched by Simulated Annealing based on a representation. To search efficiently based on representations, it is necessary to define appropriate MOVE operations. In this paper, we restrict MOVE operations so that a certain MOVE can restore any adjacent solution to former solution and confirmed the efficteveness by experiments. |
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| Title | A Hierarchical Type Segmentation Algorithm Based on Support Vector Machine for Colorectal Endoscopic Images with NBI Magnification |
| Author | *Takumi Okamoto, Tetsushi Koide, Anh-Tuan Hoang, Koki Sugi, Tatsuya Shimizu, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka (Hiroshima University, Japan) |
| Page | pp. 374 - 379 |
| Keyword | Support Vector Machine (SVM), Colorectal Endoscopic Images, Computer-Aided Diagnosis (CAD), Hierarchical Type Segmentation, FPGA |
| Abstract | With the increase of colorectal cancer patients in recent years, the needs of quantitative evaluation of colorectal cancer are increased, and the computer-aided diagnosis (CAD) system which supports doctor's diagnosis is essential. In this paper, a hardware design of type identification module in CAD system for colorectal endoscopic images with narrow band imaging (NBI) magnification is proposed for real-time processing of full high definition image (1920 x 1080 pixel). A pyramid style identifier with SVMs for multi-size scan windows, which can be implemented with small circuit area and achieve high accuracy, is verified for actual complex colorectal endoscopic images. |
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| Title | High Performance Feature Transformation Architecture Based on Bag-of-Features in CAD System for Colorectal Endoscopic Images |
| Author | *Koki Sugi, Tetsushi Koide, Anh-Tuan Hoang, Takumi Okamoto, Tatsuya Shimizu, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka (Hiroshima University, Japan) |
| Page | pp. 380 - 385 |
| Keyword | Colorectal Endoscopic Images, Computer-Aided Diagnosis(CAD), Feature Transformation, Visual Word(VW), FPGA Hardware Implementation |
| Abstract | Our research describe the computer-aided diagnosis (CAD) system for colorectal endoscopic images with narrow band imaging (NBI) magnification, which identifies a pathology type from local feature in the NBI endoscopic image. We propose a high speed feature transformation for CAD system by using Manhattan distance calculation and on the fly normalization method. A high performance and a low cost algorithm for multiple Scan Window (SW) processing for FPGA is also introduced. The proposed high speed feature transformation can be completed within about 380 msec on a real time Full HD NBI endoscopic image. |
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| Title | Hardware Implementation of Motion Estimation Technology Using High Level Synthesis and Investigations into Techniques for Improvements |
| Author | *Shota Nagai (Graduate School of Science and Engineering, Kindai University, Japan), Takashi Kambe (Depart. of Electric and Electronic Engineering, Kindai University, Japan), Gen Fujita (Osaka Electro-Communication University, Japan) |
| Page | pp. 386 - 390 |
| Keyword | motion estimation, H.264/AVC, EPZS, high level synthesis, Bach C |
| Abstract | The motion estimation technology that is a key part of the H.264/AVC (Advanced Video Coding) standard, implemented it as hardware using high-level synthesis technology, and investigated improvements. An EPZS algorithm was implemented instead of a Full Search algorithm, and the results evaluated to understand the effectiveness of the high-level synthesis technology and of the speedup techniques that were adopted. |
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| Title | FPGA Oriented Intra Angular Prediction Image Generation Hardware for HEVC Video Coding |
| Author | *Eita Kobayashi, Seiya Shibata (NEC Corporation, Japan), Noriaki Suzuki (NEC corporation, Japan), Atsufumi Shibayama (NEC Corporation, Japan), Takeo Hosomi (NEC Coporation, Japan) |
| Page | pp. 391 - 396 |
| Keyword | HEVC, FPGA, Architecture, High Level Synthesis |
| Abstract | This work proposes a novel architecture for intra prediction image generation of High Efficiency Video Coding (HEVC) standards oriented to FPGA. HEVC intra prediction is highly-extended from H.264 in those of mode and block size to realize the high flexibility. From the point of view of hardware, however, this flexibility cause an increasing required the number of MUXs although MUXs tend to be a bottleneck of area and frequency in the case of FPGA. In this paper we propose a Reshaping Buffered Architecture which enables reduction the number of MUXs, drastically. Experimental results show that our proposed architecture can reduce up to 70% of number of MUXs compared with raster scan based architecture. This resulted in a marked improvement of maximum frequency by 43% and LUT usage by 51%, respectively. |
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| Title | High Accuracy and Simple Real-Time Circle Detection on Low-Cost FPGA for Traffic-Sign Recognition on Advanced Driver Assistance System |
| Author | *Anh-Tuan Hoang (Research Institute for Nanodevice and Bio Systems, Hiroshima University, Japan), Masaharu Yamamoto (Graduate School of Advanced Sciences of Matter, Hiroshima University, Japan), Tetsushi Koide (Research Institute for Nanodevice and Bio Systems, Hiroshima University, Japan) |
| Page | pp. 397 - 402 |
| Keyword | circle detection, traffic sign detection, pipeline scaning, ADAS, multi grain pipelining |
| Abstract | This paper describes a hardware oriented algorithm and its conceptual implementation for real-time traffic signs detection system on automotive oriented FPGA. The speed limit sign area on a grayscale video frame is detected through a two-stage simple computation process. Rectangle Pattern Matching roughly detects global luminosity sharing feature between rectangle and circle for Region of Interest (ROI). Then, Circle Detection roughly votes local pixel direction of circle inside the detected ROI in binary image for circle confirmation. The proposed system achieves 83 full HD fps and over 99% accuracy even in difficult situation such as rainy night. It occupies around 50% the hardware available on proposed Xilinx Zynq automotive FPGA, which has 85 K logic cells, 53.2 K LUTs, 106.4 K registers and 506 KB BRAM, and so be able to apply to Advanced Driver Assistance System on common vehicles. |
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| Title | DMATP: A Design Method and Architecture of TU Parallel Processing for 4K HEVC Hardware Encoder |
| Author | *Seiya Shibata, Eita Kobayashi, Noriaki Suzuki, Atsufumi Shibayama, Takeo Hosomi (NEC, Japan) |
| Page | pp. 403 - 408 |
| Keyword | HEVC, hardware design |
| Abstract | This paper proposes design method and architecture of parallel processing hardware for Transform Units in High Efficiency Video Coding (HEVC). HEVC is the next generation video coding standard which is expected to be used for high resolution broadcasting such as 4K UltraHD. Since HEVC introduces higher complexities and dependencies than previous standard H.264/AVC, hardware designers have to find and utilize parallelism in HEVC to realize strict real-time encoding performance especially for broadcasting purpose. We propose design method to find appropriate parallelism considering both HEVC algorithm and hardware resources focusing on the Transform Units processing, and propose architecture to bring the parallelism efficiently. With the architecture, we got a prospect of realizing 4K HEVC encoder. |
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| Title | An Improved Rate-Distortion Optimized Quantization Algorithm and Its Hardware Implementation |
| Author | *Genki Moriguchi (Graduate School of Science and Engineering, Kindai University, Japan), Takashi Kambe (Depart. of Electric and Electronic Engineering, Kindai University, Japan), Gen Fujita (Osaka Electro-Communication University, Japan) |
| Page | pp. 409 - 414 |
| Keyword | H.264/AVC, RDOQ, function based pipelining, high-level synthesis, Bach C |
| Abstract | Rate-distortion optimized quantization (RDOQ) is an important technology in H.264/AVC for improving video coding performance. It is able to determine the optimal value among multiple quantization candidates based on rate-distortion (RD). We propose improvements to the algorithm to reduce its complexity by changing the bit-rate estimation method and by excluding low scored candidates for the quantization. We also implement the algorithm in hardware using the Bach C high-level synthesis tool. Finally, the performances of the proposed algorithm and hardware design results are evaluated. |
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| Title | Implementation and Evaluation of AES/ADPCM on STP and FPGA with High-Level Synthesis |
| Author | *Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya University, Japan) |
| Page | pp. 415 - 420 |
| Keyword | FPGA, DRP, High-level synthesis |
| Abstract | Reconfigurable techniques are attracting attention as an alternative to dedicated hardware of SoC. We have evaluated FPGA and STP engine in order to confirm their performance whether they can substitute the dedicated hardware of SoC. We selected AES and ADPCM applications to compare the performance of FPGA and STP engine. The applications were synthesized with the same high-level synthesis tools. Then, we implemented them onto FPGA and STP engine using the integrated development environments. For the evaluation, we compared them in terms of resource usage, the number of states, the number of cycles, frequency, and execution time. |
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| Title | Speed Traffic-Sign Number Recognition on Low Cost FPGA for Robust Sign Distortion and Illumination Conditions |
| Author | *Masaharu Yamamoto, Anh-Tuan Hoang, Tetsushi Koide (Hiroshima University, Japan) |
| Page | pp. 421 - 426 |
| Keyword | Advanced Driver Assistance System (ADAS), Real-Time Processing, Traffic-Sign Detection, Number Recognition, FPGA Imprementation |
| Abstract | In this paper, we propose a hardware-oriented robust speed traffic-sign recognition algorithm which can process real-time for Advanced Driving Assistant System (ADAS). In difficult conditions, such as sign distortion in various angle or at night and rain, the proposed algorithm is still be able to recognize the traffic sign with high precision. The proposed hardware oriented number recognition algorithm achieves more than 99 % in recognition rate in daytime and achieves 94.2 % including difficult conditions in rainy night. |
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| Title | Efficient Manipulation of Truth Tables on CUDA for Gate-Level Simulation |
| Author | *Yuri Ardila, Tatsuyuki Kida, Shigeru Yamashita (Ritsumeikan University, Japan) |
| Page | pp. 427 - 432 |
| Keyword | logic circuit, verification, simulator, cuda, gpu |
| Abstract | Efficient logic circuit simulations are indispensable for manufacturing LSI products. Since the computation of such simulations is usually very time consuming, there have been many efforts to optimize it; and many researches have been succeeded by using the GPGPU (General-Purpose computing on Graphics Processing Unit) technology for a decade. This paper also studies how to utilize GPGPU to optimize the logic circuit simulation. Our method is mainly based on efficient parallel manipulations of truth tables. Our idea is different from most of the previous works considering a fact that the outputs of many gates can be evaluated in parallel. We achieved as much as 65.5 times speedup compared to the simulation using only a CPU. |
| Title | Scan-Based Side-Channel Attack Implementation Evaluation on the LED Cipher Using SASEBO-GII |
| Author | *Huiqian Jiang, Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa (Waseda University, Japan) |
| Page | pp. 433 - 434 |
| Keyword | Side-Channel Attack, Scan-Based Attack, LED Cipher, SASEBO-GII, Implementation Evaluation |
| Abstract | LED is a lightweight block cipher which is suitable for both hardware and software. Design-for-test is essential to LSI designers in order to check whether devices work correctly. One of design-for-test techniques using scan chains is called scan-path test, in which testers can observe and control registers inside an LSI chip directly. Recently, scan-based side-channel attack is reported which retrieves the secret information from a cryptosystem using scan chains. In this paper, we demonstrate that the secret key in LED cipher can be retrieved successfully from the SASEBO-GII, side-channel attack standard evaluation board. Experiments show that scan-based attack is practical enough. |
| Title | A Study on Visualization of Auscultation-Based Blood Pressure Measurement |
| Author | *Yusuke Katsuki, Mingyu Li, Qing Dong, Shigetoshi Nakatake (The University of Kitakyushu, Japan) |
| Page | pp. 435 - 436 |
| Keyword | Sensor, Medical, digital filtering |
| Abstract | Blood pressure measurement by Korotkov sounds auscultation is an essential skill for health care workers, but the skill mastery is not easy because complicated tasks such as simultaneous auscultation, manipulation of pressure, and checking of scale are required. This work provides a system to visualize the Korotkov sounds and pressure-in-cuff by sensing them at the same time. Plus, we evaluate the system from the viewpoint of an educational assistance of the skill mastery of blood pressure measurement. |
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