| Title | A Novel Fast and Accurate Hot Spot Detection Method with Prüfer Code Layout Encoding |
| Author | *Hong-Yan Su, Chieh-Chu Chen, Yih-Lang Li (National Chiao Tung University, Taiwan), An-Chun Tu, Chuh-Jen Wu, Chen-Ming Huang (Taiwan Semiconductor Manufacturing Company, Taiwan) |
| Page | pp. 2 - 7 |
| Keyword | Design for manufacturability, process hotspot, pattern matching, centerline, Prüfer Encoding |
| Abstract | As design-for-manufacturability techniques have become widely used to improve the yield of nano-scale semiconductor technology in recent years, hot-spot detection methods have been investigated with a view to calibrating layout patterns that tend to reduce yield. In this work, we propose two graph models, i.e., skeleton graph and space graph, to formulate polygon topology and spatial relationship among polygons. In addition, a Prüfer Encoding based method is presented to encode each skeleton graph. Single polygon matching problem is then equivalent to the verification of graph isomorphism, which is realized by checking the identity of two correspond-ing enhanced Prüfer codes. A branch-and-bound based pattern anchoring algorithm is presented to resolve the vertex ordering problem for isomorphism checking. Finally, the general exact pattern matching problem can be accom-plished by adopting the space graph to identify the similarity of spatial rela-tionship among polygons. Experimental results show that we can achieve 5.6x runtime speedup than design-rule-based methodology in average. |
| Title | Implementation of Protocol Independent Control-Intensive Design in High-Level Synthesis |
| Author | Tung-Hua Yeh, Jen-Chieh Yeh (Industrial Technology Research Institute, Taiwan), *Qiang Zhu (Cadence Design Systems, Japan) |
| Page | pp. 8 - 12 |
| Keyword | design experiences, high-level synthesis |
| Abstract | High-level synthesis (HLS) has previously been applied to a variety of datapath-dominated and algorithmic designs achieving a comparable quality of result (QoR) with hand-edited RTL designs. However the capability and the applicability of HLS to control-intensive designs were always challenging. In this paper we present an efficient strategy to abstract control-intensive designs to which HLS technologies can efficiently be applied. The design using this strategy not only achieves good QoR, but also improves design reusability and productivity. We demonstrated two control-intensive designs: a Direct Memory Access (DMA) controller and a NAND flash controller, which resulted in a 3X design productivity improvement compared to traditional RTL design methodology, while maintaining comparable design quality to hand-edited RTL designs. |
| Title | Evaluation of On-Chip Decoupling Capacitor's Effect on AES Cryptographic Circuit |
| Author | *Tsunato Nakai, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino (Ritsumeikan University, Japan) |
| Page | pp. 13 - 18 |
| Keyword | Side-channel attack, Electromagnetic analysis, ASIC semi-custom design, Cryptographic circuit, On-chip capacitor |
| Abstract | Power Analysis (PA) attack and Electromagnetic Analysis (EMA) attack reveal a secret key on cryptographic circuits by measuring power variation and electromagnetic radiation during cryptographic operations, respectively. Inserting decoupling capacitors reduces PA leak; however, a resistance against EMA attack is not well-known. We fabricated Advanced Encryption Standard (AES) cryptographic chips with and without on-chip decoupling capacitors, and evaluated the resistance against PA and EMA attack. This paper presents on-chip decoupling capacitors make vulnerable to the EMA attack using Hamming-weight model. |
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| Title | A Design of CMOS On-Chip Photovoltaic Device and Regulated DC-DC Converter for Micro System |
| Author | *Haruki Ono, Kazuki Nomura, Nobuhiko Nakano (Keio University, Japan) |
| Page | pp. 25 - 27 |
| Keyword | stand-alone micro system, photovoltaic device, bootstrap charge pump |
| Abstract | In this paper, we propose electric power system for a stand-alone micro system. The micro system consists of photovoltaic device, voltage boost, ring oscillator, and regulator on a single silicon chip. We designed and measured several types of photovoltaic devices. The maximum output voltage of photovoltaic device is 550mV. The bootstrap charge pump circuit and regulator are designed for this power supply. This power supply outputs more than 1V. It is enough voltage for standard CMOS circuit. |
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| Title | An Error Diagnosis Technique Using QBF Solver to Fix LUT Functions |
| Author | *Naoki Katayama, Hiroyuki Sakamoto, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe University, Japan) |
| Page | pp. 28 - 33 |
| Keyword | error diagnosis, ECO, QBF |
| Abstract | This paper presents an error diagnosis technique using a QBF (Quantified Boolean Formula) solver to fix LUT functions. Although the conventional SAT-based error diagnosis technique checks equivalence between the given specification and the rectified circuit for every assignment to truth variables with each LUT function, the proposed QBF-based technique obtains all assignments to truth variables for satisfying equivalence at a time. Experimental results have shown that the proposed technique rectifies circuits which were unable to be corrected by the conventional SAT-based technique. |
| Title | Energy-Efficient Dynamic Voltage and Frequency Scaling by P/N-Performance Self-Adjustment Using Adaptive Body Bias |
| Author | *A.K.M. Mahfuzul Islam, Norihiro Kamae, Tohru Ishihara, Hidetoshi Onodera (Kyoto University, Japan) |
| Page | pp. 34 - 39 |
| Keyword | DVFS, Energy Efficiency, Process Variation, Adaptive Body Bias |
| Abstract | Dynamic voltage and frequency scaling (DVFS) is a promising technique to
improve energy efficiency for heterogeneous systems where work load varies
with time. This paper addresses the effects of process variation on the
energy efficiency for wide voltage range DVFS and proposes the use of P/N-performance self-adjustment scheme to enable typical-case design.
Simulation results show that energy efficiency can be improved by more
than 100% with the proposed technique compare to the conventional worst-case design methodology for a 65-nm commercial process. |
| Title | A Nested Loop Pipelining in C Descriptions for System LSI Design |
| Author | *Masahiro Nambu, Takashi Kambe (Kinki University, Japan), Shuji Tsukiyama (Chuo University, Japan) |
| Page | pp. 40 - 43 |
| Keyword | nested loop, pipelining, C based design, high level synthesis, BACH sytem |
| Abstract | Behavioral synthesis from C language is now a key technology of system LSI design.
Since large streaming data are usually processed by nested loops in behavioral description of system LSI, it is important to synthesize a circuit which can process such data efficiently.
Nested loop pipelining is a useful implementation technique of the description to synthesize a circuit such that both computational throughput and hardware utilization are maximized.
In this paper, we propose an algorithm for nested loop pipelining, which can produce pipeline stages with different processing times.
We show two practical experimental results in order to demonstrate the performance of the proposed algorithm. |
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| Title | Memory Management for Dual-Addressing Memory Architecture |
| Author | *Ting-Wei Hong, Yen-Hao Chen, Yi-Yu Liu (Yuan Ze University, Taiwan) |
| Page | pp. 50 - 55 |
| Keyword | Dual-addressing memory, 2D virtual memory management, Data granularity and indexing |
| Abstract | Dual-addressing memory architecture is designed for two-dimensional memory access with both row-major and column-major localities. In this
paper, we highlight two memory management issues in dual-addressing memory. First, to avoid the external fragmentation, we propose a virtual dual-addressing memory design to enable memory management via operating system. After that, to deal with the size mismatch between user-defined data and dual-addressing memory, we discuss data arrangement policies for different data granularity. With the proposed memory management techniques, we are capable of maximizing the memory utilization of dual-addressing memory. |
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| Title | Alpha-Gamma Data Compression Method for Artificial Vision Systems Using Visual Cortex Stimulation |
| Author | *Tomoki Sugiura, Arif Ullah Khan, Yoshinori Takeuchi, Masaharu Imai (Osaka University, Japan) |
| Page | pp. 56 - 61 |
| Keyword | data compression, artificial vision, hybrid organ |
| Abstract | In this paper a data compression method for visual cortex stimulation based artificial vision is proposed and evaluated. The proposed method uses run-length encoding to express visual cortex stimulus data in numerical form, in which the numerical data representing 1 data and 0 data are encoded into binary by alpha encoding and gamma encoding, respectively.
From experimental results, the proposed method reduced data size approximately 83% while execution cycles of the proposed method is practically equal to gamma encoding. |
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| Title | An Efficient Test Pattern Generator -Mersenne Twister- |
| Author | Hiroshi Iwata, *Sayaka Satonaka, Ken'ichi Yamaguchi (Nara National College of Technology, Japan) |
| Page | pp. 62 - 67 |
| Keyword | Mersenne Twister, manufacturing test, pseudo random pattern, built-in self test, fault coverage |
| Abstract | Built-in self test (BIST) is an answer for a high reliable manufacturing test with a reasonable cost. In this paper, we supposed that the Mersenne Twister is used as the test pattern generator instead of the LFSR to implement BIST into VLSIs. Experimental results show that the test patterns generated through the Mersenne Twister are efficient with respect to the fault coverage and it is implemented with a comparable cost to the LFSR. |
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| Title | Power Optimization of a Micro-Controller with Silicon on Thin Buried Oxide |
| Author | *Kuniaki Kitamori, Hongliang Su, Hideharu Amano (Keio University, Japan) |
| Page | pp. 68 - 73 |
| Keyword | SOTB, V850E-Star, low power consumption |
| Abstract | Nowadays, from battery supplied mobile devices to supercomputers, reducing the power consumption has become a serious design issue. Although using low power supply is the most efficient way to reduce the power, it also increase the leakage power and delay variance. Low-power Electronics Association & Project(LEAP) developed Silicon On Thin Buried Oxide(SOTB) technology to solve those problems. In order to verify the SOTB technology, we have applied to an automotive microcontroller V850E-Star. In this report, we investigate the operational speed and leak power with 40 kinds of reverse bias and forward bias voltages for each purpose: standby, energy maximum and performance maximum. In the standby mode, leak power of the energy maximum mode is reduced by 92%, while it works with 33MHz frequency clock in the energy maximum mode. |
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