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Monday April 3, 2006
| Title | Networked Embedded Systems: Sensor Nets and Beyond |
| Speaker | Shankar Sastry (Univ. of California, Berkeley, United States) |
| Title | System Level Specification Synthesis |
| Author | Mikito Iwamasa, Tadatoshi Ishii, Kazuko Yamamoto (InterDesign Technologies, Inc., Japan) |
| Title | Communication Interfaces for System Level Design |
| Author | Hideaki Minamide, Tadashi Yoshimoto (Mitsubishi Electric Corprration, Japan), Yoshiaki Takagi, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ., Japan) |
| Title | High-Level Synthesis of Variable Accesses and Function Calls in Software Compatible Hardware Synthesizer CCAP |
| Author | Masanari Nishimura, Kenichi Nishiguchi, Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Hiroyuki Kanbara (ASTEM RI, Japan), Hiroyuki Tomiyama (Nagoya Univ., Japan), Yutetsu Takatsukasa, Manabu Kotani (Kyoto Univ., Japan) |
| Title | Refinement of Communication Architecture and Generation of Target Software with SystemC |
| Author | Matthias Krause, Oliver Bringmann, Wolfgang Rosenstiel (FZI Forschungszentrum Informatik, Germany) |
| Title | A program structure retaining analysis for hardware assistance |
| Author | Yuichi Shirai, Masanori Nishizawa, Takaaki Suzuki, Hiroshige Tsugawa, Hironori Yamauchi (Ritsumeikan Univ., Japan), Hideo Nishikado (Fukui Univ., Japan), Shiro Kobayashi (Asahi Kasei Co., Japan) |
| Title | Exploiting Narrow Bitwidth Operations for Low Power Embedded Software Design |
| Author | Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ., Japan) |
| Title | SoC-CBSHVE: a System-On-Chip Software and Hardware Co-Verification Environment Based on Components |
| Author | JinShan Yu, YaoHong Zhang, QingPin Tan, Tun Li (National Univ. of Defense Technology, China) |
| Title | Design and Implementation of a Co-Emulation Environment with High Portability and Usability |
| Author | Khamphong Khongsomboon, Nobuyuki Kondoh, Masashiro Ohyama, Naohiko Shimizu (Tokai Univ., Japan) |
| Title | Three Techniques about Memory to Speed Up Function Verification |
| Author | Kouhei Hosokawa, Katsunori Tanaka, Soji Mori, Yuichi Nakamura (NEC, Japan) |
| Title | Cooperative Simulation Environment of Hardware Plugged into a DIMM slot |
| Author | Tetsu Izawa, Konosuke Watanabe, Akira Kitamura, Yasuo Miyabe, Tomotaka Miyasiro, Hideharu Amano (Keio Univ., Japan) |
| Title | Flexible Hardware/Software Interface Modeling Using High Level service Based Component Model |
| Author | Lobna Kriaa, Adriano sarmento, Mohamed-Wassim Youssef, Aimen Bouchhima, Frederic Petrot, Ahmed Amine Jerraya (TIMA Laboratory, France), Anne-Marie Fouillart (Thales, Land & Joint Systems EDS/DHD, France) |
| Title | C-Based design of A Particle Tracking System |
| Author | Kenichi Jyoko, Takahiro Ohguchi, Hirokazu Uetu, Koji Sakai (Kinki Univ., Japan), Takanori Ohkura (JST Mfg. Co., Ltd., Japan) |
| Title | Hardware Architecture of Efficient Message-Passing Schedule based on Modified Min-Sum Algorithm for Decoding LDPC Codes |
| Author | Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto (Waseda Univ., Japan) |
| Title | Performance Comparison and Optimization of Various LDPC Decoders |
| Author | Yun-Nan Chang (National Sun Yat-sen Univ., Taiwan) |
| Title | FPGA-Based Design of a Surveillance System Employing Optical Flow |
| Author | Jason Schlessman (Princeton Univ., United States), Burak Ozer (Verificon Co., United States), Kenji Fujino, Kazurou Itoh (Yokogawa Electric Co., Japan), Wayne Wolf (Princeton Univ., United States) |
| Title | Minimum Euclidean Distance Associative Memory Architecture with Fully-Parallel Search Capability |
| Author | Md. Anwarul Abedin, Kazuhiro Kamimura, Ali Ahmadi, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ., Japan) |
| Title | Efficient Constrained Stimuli Generation for Biased Random Simulation |
| Speaker | Andreas Kuehlmann (Cadence Berkeley Labs, United States) |
| Title | Reversible Logic Synthesis of Sequential Elements |
| Author | Min-Lun Chuang, Chun-Yao Wang (National Tsing Hua Univ., Taiwan) |
| Title | Optimal Register Merging Method after Register Relocation in Semi-Synchronous framework |
| Author | Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech., Japan) |
| Title | Peak Current Reduction Technique by Flip-Flop Replacement |
| Author | Jiun-Kuan Wu, Tsung-Yi Wu (National Changhua Univ. of Education, Taiwan) |
| Title | Design of Address Generators Using multiple LUT cascade on FPGA |
| Author | Hui Qin, Tsutomu Sasao (Kyushu Inst. of Tech., Japan) |
| Title | Arithmetic Module Generator Based on Arithmetic Description Language |
| Author | Yuki Watanabe, Naofumi Homma, Takafumi Aoki (Tohoku Univ., Japan), Tatsuo Higuchi (Tohoku Inst. of Tech., Japan) |
| Title | Improved Clustered Voltage Scaling Technique via Better Power-Timing Slack Sensitivity Strategy |
| Author | Hsiuan-Yi Tan, Hung-Ming Chen (National Chiao Tung Univ., Taiwan) |
| Title | Performance of H-tree Clock Distribution Networks in Presence of Process Variations and Inductance Effects |
| Author | Zhang Xu, Jiang Xiaohong, Susumu Horiguchi (Tohoku Univ., Japan) |
| Title | A Unified C-BiCMOS Buffer Driver Using CMOS/SOI Process for High Speed and Low Energy Operation |
| Author | Takashi Hamahata, Toshiro Akino (Kinki Univ., Japan) |
| Title | Low-Power Design of CML Drivers for On-Chip Transmission-Lines |
| Author | Akira Tsuchiya, Takeshi Kuboki, Hidetoshi Onodera (Kyoto Univ., Japan) |
| Title | Power Reduction Using On-Chip Transmission Line for 45nm technology |
| Author | Kenichi Okada, Takumi Uezono, Kazuya Masu (Tokyo Inst. of Tech., Japan) |
| Title | Hierarchical Power Deliver Network Analysis Via Bipartite Markov Chain |
| Author | Pei-Yu Huang, Chih-Hong Hwang, Po-Han Lai, Yu-Min Lee (National Chiao-Tung Univ., Taiwan) |
| Title | Extracting a Random Component of Variation from Measurement Results of a 90 nm LUT Array |
| Author | Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ., Japan) |
| Title | Yield Estimation Considering Via Defects |
| Author | Takumi Uezono, Kenichi Okada, Kazuya Masu (Tokyo Inst. of Tech., Japan) |
| Title | Silencer Pro: A Synthesized Compact Models-Enabled CAD Tool for Substrate Noise Analysis |
| Author | Hai Lan (Stanford Univ., United States), Matthew MacClary, Karti Mayaram, Terri Fiez (Oregon State Univ., United States), Robert W. Duttton (Stanford Univ., United States) |
| Title | Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global interconnect |
| Author | Yoichi Yuyama, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ., Japan) |
| Title | Electrical Modeling of MEMS Capacitive Sensor and Interconnections between Sensor and Circuit |
| Author | Hui Zhu, Bo Huang, Takaaki Baba (Waseda Univ., Japan) |
| Title | An Estimation Based Analog Circuit Sizing Method with Region Partitioning |
| Author | Tomohiro Fujita, Kazuki Kawasaki (Ritsumeikan Univ., Japan) |
| Title | Application Specific Processors (ASIP): On Design and Implementation Efficiency |
| Speaker | Heinrich Meyr (RWTH Aachen Univ., Germany) |
Tuesday April 4, 2006
| Title | Continuously Evolving Automobile Electronics |
| Speaker | Takashi Shigematsu (Toyota Motor Co., Japan) |
| Title | Low Power Configurable Processor Generation Method with Fine Clock Gate at Pipeline Registers and Register Files |
| Author | Hirohumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan) |
| Title | MOCSOC: Multiprocessor On Chip Synthesis from Occam |
| Author | Riad Benmouhoub, Omar Hammami (ENSTA, France) |
| Title | MOCDEX: Multiprocessor on Chip Multiobjective Design Space Exploration with Direct Execution |
| Author | Riad Benmouhoub, Omar Hammami (ENSTA, France) |
| Title | Multiple Clustered Core Processors |
| Author | Toshinori Sato (Kyushu Univ., Japan), Akihiro Chiyonobu (Kyushu Inst. of Tech., Japan) |
| Title | Performance and Energy Efficient Data Cache Architecture for Embedded Simultaneous Multithreading Microprocessor |
| Author | Chengjie Zang (Waseda Univ., Japan), Shigeki Imai (Sharp Co., Japan), Shinji Kimura (Waseda Univ., Japan) |
| Title | Optimal Instruction Scheduling for Processors with Partial Forwarding using Integer Programming |
| Author | Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan) |
| Title | Instruction Compression Based on Field-Partitioning and an Efficient Pipelined Decompression System |
| Author | Yuan-Long Jeang, Yong-Zong Lin (National Kaohsiung Univ. of Applied Sciences, Taiwan) |
| Title | A Pipelined Functional Unit Generation Method in HW/SW Cosynthesis System for SIMD Processor Cores |
| Author | Shunitsu Kohara, Akira Kurihara (Waseda Univ., Japan), Yuichiro Miyaoka (Waseda Univ., presently, the author is with the Toshiba., Japan), Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ., Japan) |
| Title | Removal of Operation Overlap during Scheduling in High Level Synthesis |
| Author | Liangwei Ge, Kouhei Isoda, Takeshi Yoshimura (Waseda Univ., Japan) |
| Title | Buffer Minimization In RTL Synthesis From Coarse-grained Dataflow Specification |
| Author | Hoeseok Yang (Seoul National Univ., Republic of Korea), Hyunuk Jung (SAMSUNG Electronics Co., LTD., Republic of Korea), Soonhoi Ha (Seoul National Univ., Republic of Korea) |
| Title | Schedule Exploration for Minimizing Energy Consumption by Data Communications |
| Author | Kazuhito Ito (Saitama Univ., Japan) |
| Title | Simultaneous control-step and skew assignment for control signals in RT-level datapath synthesis |
| Author | Takayuki Obata, Mineo Kaneko (JAIST, Japan) |
| Title | Domain-Specific Reconfigurable Architecture for Media Processing |
| Author | Yukio Mitsuyama, Kazuma Takahashi, Rintaro Imai, Takao Onoye (Osaka Univ., Japan), Isao Shirakawa (Univ. of Hyogo, Japan) |
| Title | Fault-Tolerant Dynamic-Reconfigurable Device based on EDAC with Rollback |
| Author | Kentaro Nakahara, Shin'ichi Kouyama (Kyoto Univ., Japan), Tomonori Izumi (Ritsumeikan Univ., Japan), Hiroyuki Ochi, Yukihiro Nakamura (Kyoto Univ., Japan) |
| Title | Execution Schemes for Dynamically Reconfigurable Architectures |
| Author | Tobias Oppold, Thomas Schweizer, Julio Oliveira Filho, Sven Eisenhardt, Tommy Kuhn, Wolfgang Rosenstiel (Univ. of Tuebingen, Germany) |
| Title | Online Task Placement on Partially Reconfigurable FPGAs using I/O Routing Information |
| Author | Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita (NAIST, Japan), Kazuo Nakajima (Univ. of Maryland, Japan), Katsumasa Watanabe (NAIST, Japan) |
| Title | Novel Algorithms for the Exact Computation of Storage Requirements Based on the Decomposition of Integral Polyhedra |
| Author | Ilie I. Luican, Hongwei Zhu, Florin Balasa (Univ. of Illinois, Chicago, United States) |
| Title | Present Status and Future Trend of Power/Signal Integrity Analysis |
| Speaker | Hideki Asai (Shizuoka Univ., Japan) |
| Title | Satisfiability Checking under Equivalence Constraints for a Decidable Subclass of First-Order Logic |
| Author | Hiroaki Kozawa, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ., Japan) |
| Title | Formal Combinational Equivalence Checking Using Probability |
| Author | Shih-Chieh Wu, Chun-Yao Wang, Jan-An Hsieh (National Tsing Hua Univ., Taiwan) |
| Title | Exploiting K-Distance Signature for Boolean Matching and G-Symmetry Detection |
| Author | Kuo-Hua Wang (Fu Jen Catholic Univ., Taiwan) |
| Title | Finding Simple Disjoint Decompositions on Sets of Combinations Based on Zero-suppressed BDDs |
| Author | Shin-ichi Minato (Hokkaido Univ., Japan) |
| Title | MUX Graph based False Path Analysis for Large Logic Circuits |
| Author | Hiroyuki Higuchi (Fujitsu Laboratories Ltd, Japan), Yusuke Matsunaga (Kyushu Univ., Japan) |
| Title | A parallel implementation of a genetic algorithm-based floorplanning method on PC clusters |
| Author | Takayoshi Shimazu, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ., Japan) |
| Title | Improved Neighborhood Exchange in Multilevel Large-Scale Modules Floorplanning/Placement |
| Author | Kuan-Chung Wang, Hung-Ming Chen (National Chiao Tung Univ., Taiwan) |
| Title | Network-Flow Based Delay-Aware Partitioning Algorithm |
| Author | Masato Inagi (Univ. of Kitakyushu, Japan), Atsushi Takahashi (Tokyo Inst. of Tech., Japan) |
| Title | Function Smoothing of Half-Perimeter Wirelength in Analytical Placement |
| Author | Chen Li, Cheng-Kok Koh (Purdue Univ., United States) |
| Title | Crosstalk-Driven Placement with Considering On-Chip Mutual Inductance and RLC Noise |
| Author | Cheng-Hsuan Chiu, Chih-Hong Hwang, Zhe-Yu Lin, Yu-Min Lee (National Chiao Tung Univ., Taiwan) |
| Title | A Fast Algorithm in Constructing Performance-Driven Buffered Interconnect Tree with Routing Blockage Consideration |
| Author | Tsung-Ta Yu, Hung-Ming Chen (National Chiao Tung Univ., Taiwan) |
| Title | Performance- and Congestion-Driven Multilevel Router |
| Author | Yih-Lang Lin, Chih-Hong Hwang, Yu-Min Lee (National Chiao-Tung Univ., Taiwan) |
| Title | A Power Grid Optimization Algorithm with Consideration of Dynamic Circuit Operations |
| Author | Hironobu Ishijima, Taiki Harada, Kenji Kusano, Masahiro Fukui, Masaya Yoshikawa, Hidekazu Terai (Ritsumeikan Univ., Japan) |
| Title | Timing-Driven Octilinear Steiner Tree Construction Based on Steiner-Point Reassignment |
| Author | Jin-Tai Yan, Chia-Fang Lee, Ming-Ching Huang (Chung-Hua Univ., Taiwan) |
| Title | Minimum-Crosstalk Track Assignment with Efficient Track Utilization |
| Author | Meng-Xin Jiang, Ying-Shu Luo, Yih-Lang Li (National Chiao Tung Univ., Taiwan) |
| Title | Post-Routing Yield/Reliability Improvement by Redundant Via Insertion and End-line Extension |
| Author | Kuang-Yao Lee, Ting-Chi Wang (National Tsing Hua Univ., Taiwan) |
| Title | Role of University Researches under Land-sliding CMOS Silicon Age |
| Organizer | Takahide Inoue (BA Consulting Group & CITRIS, United States) |
| Moderator | Takahide Inoue (BA Consulting Group & CITRIS, United States) |
| Panelists | (tentative) Hideki Asai (Shizuoka Univ., Japan), Andreas Kuehlmann (Cadence Berkeley Labs, United States), Heinrich Meyr (RWTH Aachen Univ., Germany), Shankar Sastry (Univ. of California, Berkeley, United States) |