| Title | A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability |
| Author | *Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka University, Japan) |
| Page | pp. 233 - 237 |
| Keyword | body bias, forward bias, layout style, speed controllability |
| Abstract | Body-biasing is expected to be a common
design technique, and then area efficient implementation
in layout has been demanded. Body-biasing outside
standard cells is one of possible layouts, but in this
case body-bias controllability, especially when forward
bias is applied, is a concern. To investigate the controllability,
we fabricated a ring oscillator in a 90nm
technology, and measured the controllability. Our measurement
result and evaluation of area efficiency reveal
that body-biased circuits can be implemented with area
overhead of less than 1%. |
| Title | Simulations of Flicker Noise in SiGe HMOS: Body Bias Dependence |
| Author | *C.-Y. Chen, Y. Liu, R. W. Dutton (Stanford University, United States), J. Sato-Iwanaga, A. Inoue, H. Sorada (Matsushita Electric Industrial Co., Ltd, Japan) |
| Page | pp. 238 - 241 |
| Keyword | TCAD, flicker noise, SiGe, p-type hetero-structure MOS (pHMOS), body bias |
| Abstract | Advanced TCAD simulation capabilities have been developed to investigate flicker noise behavior in p-type SiGe/Si hetero-structure MOS (HMOS) transistors. The numerical model is based on the impedance field method and accounts for the carrier number fluctuation due to trap/de-trap effects and the correlated mobility fluctuation mechanism. Such a device-level simulation approach enables separate treatment of the buried and parasitic surface channels which have different contributions from the mobility fluctuations. Simulations have been conducted to explain experimentally observed strong body-bias dependence of drain current noise in p-HMOS devices. In particular, this dependence is found to be closely correlated with the carrier distribution between the two channels. An improved compact model to account for this body bias dependence of flicker noise in SiGe pHMOS devices is also presented in this paper. |
| Title | Active Body-Biasing Control on PD-SOI for Dual Supply Voltage Scheme |
| Author | *Yosuke Torii, Kenji Hamada, Kayoko Seto, Masaaki Iijima, Masahiro Numa (Kobe University, Japan), Akira Tada, Takashi Ipposhi (Renesas Technology Corporation, Japan) |
| Page | pp. 242 - 245 |
| Keyword | low power, active body-bias, dual supply voltage, PD-SOI |
| Abstract | The dual supply voltage scheme reduces the power consumption without performance degradation by using two power supply rails. However, an increase in the delay has made assigning the lower supply voltage more difficult in the conventional dual-VDD scheme under low supply voltage. We propose a technique for dual-VDD scheme employing the Active Body-biasing Control on PD-SOI, which increases the number of VDDL-cells by lowering threshold voltage. Simulation results have shown our approach reduces the power consumption at low voltage operation. |
| Title | A Look-Ahead Active Body-Biasing Scheme for SOI-SRAM with Dynamic VDDM Control |
| Author | *Kayoko Seto, Yosuke Torii, Masaaki Iijima, Masahiro Numa (Kobe University, Japan), Akira Tada, Takashi Ipposhi (Renesas Technology Corporation, Japan) |
| Page | pp. 246 - 249 |
| Keyword | PD-SOI, body-bias, SRAM, low power design |
| Abstract | Instability of SRAM memory cells derived from aggressive technology scaling has become one of the most significant issues. Although lowering the supply voltage for a memory cell (VDDM) improves a write margin, which increases the access time. In this paper, we propose a memory cell employing a Look-ahead Active Body-biasing (LAB) scheme for SOI-SRAM with dynamic VDDM control. Simulation results have shown that the proposed SRAM cell shortens the access time by 54 % in the write mode. |
| Title | A Study on Variation-Component Decomposition using Polynomial Smoothing Function |
| Author | *Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu (Tokyo Institute of Technology, Japan) |
| Page | pp. 250 - 255 |
| Keyword | device variation, systematic, random, goodness of fit, AIC |
| Abstract | A procedure that decomposes parametric device
variation into systematic and random components of the device variation
is studied. Regarding the decomposition process as obtaining a smooth
regression function, polynomial model is used to describe the systematic
variation and the residue is considered as random variation. In a
proposed flow, required order of regression function is determined
adaptively, using a statistical index called AICc. The impact of
polynomial order selection on variation competition is also discussed
through numerical experiments using measured data. |
| Title | Static-Noise-Margin Analysis of Major SRAM-Cell Types Including Production Variations for a 90nm CMOS Process |
| Author | *Shinya Izumi, Koh Johguchi, Hans Jüergen Mattausch, Tetsushi Koide (Hiroshima University, Japan) |
| Page | pp. 261 - 265 |
| Keyword | SRAM, SNM, variation, robust |
| Abstract | Here we report a comparative study of the effect of the Vth variation on the major SRAM-cell types in a 90 nm CMOS process,
namely the conventional 1-port cell with 6-transistors,
the 8- transistor cell with separate read and write port,
the static noise margin (SNM) free 7-transistor cell,
and the loadless 4-transistor cell.
While 4Tr-SRAM and 6Tr-SRAM cannot keep enough
reliability at worst case,
8Tr-SRAM and 7Tr-SRAM can keep it at worst case.
At low operation voltage, 8Tr-SRAM has higher
reliability than 7Tr-SRAM. |
| Title | Active Mode Leakage Power Reduction Based on the Controlling Value of Logic Gates |
| Author | *Lei Chen, Shinji Kimura (The Graduate School of Information, Production and Systems, Waseda University, Japan) |
| Page | pp. 266 - 271 |
| Keyword | MTCMOS, Leakage Power, Controllability |
| Abstract | Leakage power dissipation becomes an
important issue as technology scaling of LSI process. In this paper,
we propose a novel control method of Multi-Threshold CMOS (MTCMOS)
technology based on the controllability of logic gates. The
controlling value of a logic gate can stop the power of the blocks
connected to other inputs of the gate. Based on the idea, we can
control the power dynamically. This paper discusses methods to
construct and control power blocks from gate level circuit. A power
optimization idea is also introduced. The effect of the proposed
method is shown on several standard benchmark circuits. |
| Title | Structural Robustness of Datapaths against Delay-Variation |
| Author | *Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (Japan Advanced Institute of Science and Technology, Japan) |
| Page | pp. 272 - 279 |
| Keyword | High-Level Synthesis, Delay Variation, Register Assignment |
| Abstract | As the feature size of VLSI becomes smaller,
delay variations become a serious problem in VLSI design.
In this paper,
we propose a novel class of robustness
for a datapath against delay variations,
which is named structural robustness against
delay-variation (SRV),
and propose sufficient conditions
for a datapath to have SRV.
A resultant circuit designed
based on these conditions
has a larger timing margin to delay variations
than previous designs
without sacrificing effective computation time.
In addition, under any degree of delay
variations, we can always find an available
clock frequency for a datapath having SRV property
to operate correctly, which could be a
preferable characteristic in IP-based design. |
| Title | Critical Issues Regarding A Variation Resilient Flip-Flop |
| Author | Toshinori Sato (Kyushu University, Japan), *Yuji Kunitake (Kyushu Institute of Technology, Japan) |
| Page | pp. 280 - 286 |
| Keyword | variations, low-power, DVS, Razor, microprocessors |
| Abstract | Razor flip-flop (FF) is a clever technique to eliminate the supply voltage margin by exploiting circuit-level timing speculation. It combines dynamic voltage scaling technique with the error detection and recovery mechanism. This paper presents an improvement of Razor FF in removing delayed clock, which complicates timing design. It is named canary FF. This paper discusses critical issues regarding the canary FF. When the issues were solved, the canary FF would achieve 10% of power reduction by exploiting input value variations. |
| Title | An Asynchronous Single-precision Floating-point Divider and its Implementation on FPGA |
| Author | *Masayuki Hiromoto, Shin'ichi Kouyama, Hiroyuki Ochi (Kyoto University, Japan), Yukihiro Nakamura (Ritsumeikan University, Japan) |
| Page | pp. 294 - 301 |
| Keyword | IP reusability, IEEE754, low power design, digit-recurrence divider |
| Abstract | Synchronous design methodology is widely used for today's digital circuits. However, it is difficult to reuse a highly-optimized synchronous module for a specific clock frequency to other systems with different global clocks, because logic depth between FFs should be tailored for the clock frequency. In this paper, we focus on asynchronous design, in which each module works at its best performance, and apply it to an IEEE754-standard single-precision floating-point divider. In our divider, a mantissa divider is driven by a high-speed local clock and connected to pre-/post-processing modules with asynchronous interface. Our divider is ready to be built into a system with arbitrary clock frequency and achieves its peak performance and area- and power-efficiency. This paper also reports an implementation result of the proposed divider on a Xilinx FPGA. |
| Title | A Power Grid Optimization Algorithm by Direct Observation of Timing Error Risk Reduction |
| Author | *Makoto Terao, Kenji Kusano, Yoshiyuki Kawakami (Graduate School of Science and Engineering, Ritsumeikan University, Japan), Masahiro Fukui (Dept. of VLSI System Design, Ritsumeikan University, Japan), Shuji Tsukiyama (Dept. of EECE, Chuo University, Japan) |
| Page | pp. 310 - 315 |
| Keyword | delay analysis, dispersion, power and ground routing optimization, IR-drop, electro-migration |
| Abstract | With the advent of super deep submicron age, the circuit behavior has large variation according to the process variation. Power grid optimization which considers the timing error risk caused by the variation becomes very important for the stable and fast operation of the system. This paper proposes an approach which uses the “timing error risk caused by the IR drop” as its direct objective function. Experimental results shows the effectivity. |
| Title | A High-level Power Grid Optimization Algorithm by Direct Observation of Manufacturing Cost Reduction |
| Author | *Takayuki Hayashi, Hironobu Ishijima, Yoshiyuki Kawakami, Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 316 - 321 |
| Keyword | floor-plan, optimization, Cost, decoupling capacitor |
| Abstract | Recent rapid growth of the narrow and fine patterning technology faces many difficulties of power grid design. The insertions of the decoupling capacitor cause the increase of size of the blocks in the chip. It is hard to analyze the trade-off after the detail placement and routing optimization. Authors propose an approach to do the optimization in the phase of floorplanning and deals with trade-off analysis between the chip cost by area increase and stabilization of circuit behavior. |
| Title | An Evaluation of Circuit Simulation Algorithms for Hardware Implementation |
| Author | *Taiki Hashizume, Hironobu Ishijima, Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 322 - 327 |
| Keyword | circuit simulation, Euler method, Runge-Kutta method, hardware, fixed point |
| Abstract | In super deep submicron technology, a very large sized system on one LSI chip is constructed. Therefore, the circuit size becomes larger, and we need lots of time for the circuit simulation. Reducing the simulation time is indispensable for larger sized circuit design. We have proposed a high-speed circuit simulation for power supply network by hardware algorithm. The most adequate numerical analysis for hardware algorithm is specified in this paper. |