| Title | An Object-Oriented Circuit Design Method and Its Evaluation |
| Author | *Seigo Masuoka, Hiroyuki Terai, Manabu Koyama (Kinki University, Japan), Kazuhiko Nakahara (Spansion Japan Corporation, Japan), Akihisa Yamada (Sharp Corporation, Japan), Takashi Kambe (Kinki University, Japan) |
| Page | pp. 337 - 342 |
| Keyword | Object-Oriented Design, Java, Hardware-software co-design, JPEG decoder, Bach system |
| Abstract | Hardware-software System LSI solutions have increased in popularity in a variety of design domains because these systems provide both high performance and flexibility. The language used to describe the System LSI is critical in a co-design methodology because it is used in both the hardware-software design process and functional validation. Java is a general-purpose, concurrent, object-oriented, platform-independent programming language and is often used in the field of embedded system design for applications such as mobile phones. In this paper we describe the Jackal language, which is an extension of Java for hardware design and propose an object-oriented circuit design methodology based on Jackal. This methodology is applied to the design of a JPEG encoder and its performance is evaluated. |
| Title | Object Oriented Design and Synthesis of Communication in Hardware-/Software Systems with OSSS |
| Author | *Kim Grüttner, Cornelia Grabbe, Frank Oppenheimer (OFFIS - Institute for Information Technology, Germany), Wolfgang Nebel (Carl v. Ossietzky University Oldenburg, Germany) |
| Page | pp. 343 - 350 |
| Keyword | hw/sw co-design, high-level synthesis, communication synthesis, object oriented design, systemc |
| Abstract | In this paper we propose an object oriented hardware/software co-design methodology for embedded system design. The use of object-oriented techniques combined with template meta-programming during system level design facilitates the designer in writing faster, better and more reusable executable models of the specified system. One of the major challenges in system level design lies is the automatic or guided refinement process from the specification down to the implementation on a certain target platform. The contribution of this paper is a seamless communication refinement from a method based communication between active and passive objects to a signal base synthesisable communication through buses or point-to-point channels. The proposed methodology retains the separation of communication and behaviour and therefore enables an easy communication architecture exploration. To achieve this we have implemented a remote method invocation mechanism that can be used in conjunction with synthesisable channels. The applicability of our approach is shown with an IPv4 router design. |
| Title | A Data Arrangement Method for Block Floating Point Systems |
| Author | *Takashi Hamabe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka University, Japan) |
| Page | pp. 351 - 356 |
| Keyword | Block floating point, Data arrangement, Memory size |
| Abstract | Block floating point representation is a representation of real number that provides accurate arithmetic with small hardware cost. This research proposes a data arrangement method for block floating point systems considering data memory size. Our method intends to minimizes data memory size by grouping real number data which have close absolute value with an algorithm based on the Kernighan and Lin algorithm. |
| Title | Calling Software Functions from Hardware Functions in High-Level Synthesizer CCAP |
| Author | *Masanari Nishimura, Nagisa Ishiura, Yoshiyuki Ishimori (Kwansei Gakuin University, Japan), Hiroyuki Kanbara (ASTEM RI, Japan), Hiroyuki Tomiyama (Nagoya University, Japan) |
| Page | pp. 357 - 360 |
| Keyword | high-level synthesis, CCAP, hardware/software co-design, C-based design |
| Abstract | We are developing a high-level synthesizer named CCAP (C Compatible Architecture Prototyper), which synthesizes functions in C programs into hardware modules which are callable from the other software functions. In this paper, we propose a novel framework in which the synthesized hardware functions can also call software functions. We give both multi-thread and single-thread implementation schemes. We verified the correctness of the proposed method (single-thread version) through register transfer level simulation. |
| Title | Performance-Aware Communication Architecture Synthesis |
| Author | *Alexander Viehl, Oliver Bringmann (FZI Forschungszentrum Informatik, Germany), Wolfgang Rosenstiel (Universität Tübingen, Germany) |
| Page | pp. 361 - 368 |
| Keyword | Communication Architecture, Synthesis, Performance, Real-Time |
| Abstract | In this paper, a novel approach for communication architecture synthesis to guarantee conflict-free communication access in real-time critical systems is proposed. Our approach is based on the analysis of the temporal relation of communicating processes and the determination of communication instances that synchronize them. Based on these communication instances, the global system timing behavior is determined to identify potentially parallel communication instances. Based on the result of this analysis, an algorithm for determining a guaranteed conflict free communication schedule is proposed. This schedule can be used to synthesize communication controllers that realize resource allocation and guaranteed conflict-free binding of communication instances. Additionally, the inclusion of high-level communication protocols in the synthesis approach is discussed. Moreover, improvements on timing analysis are proposed with the objective of reducing the necessary amount of communication resources. |
| Title | A Network Processor Synthesis System for Task-Chaining Network Applications |
| Author | *Youhua Shi, Keishi Nakayama, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda University, Japan) |
| Page | pp. 369 - 374 |
| Keyword | network processor, synthesis, task-chaining |
| Abstract | With the rapid development of network technology, the need to design a network equipment while to offer the speed, flexibility, and ease-of-use to accelerate time-to-market has emerged. To meet this challenge, in this paper first we presented a network processor model and then based on the model we proposed a network processor synthesis system for task-chaining network applications. Unlike previous works, the proposed method has the feature of sharing the communication resources. Experimental results have shown the importance of conducting the reduction in shared resource contention and also shown that, using the proposed NP synthesis system, how we can find the optimized network processor configurations in terms of performance and area to meet the designer's requirements. |
| Title | Resynthesis Method for Circuit Acceleration on LUT-based FPGA |
| Author | *Weijie Xing (Graduate School of Information, Production and Systems, Waseda University, Japan), Takashi Horiyama (Saitama University, Japan), Shunichi Kuromaru, Tomoo Kimura (Matsushita Electric Industrial Co., Ltd, Japan), Shinji Kimura (Graduate School of Information, Production and Systems, Waseda University, Japan) |
| Page | pp. 375 - 380 |
| Keyword | Verification, acceleration, FPGA, false path |
| Abstract | Design verification becomes most time consuming part in the design period, and the reduction is important. In the paper, we focus on the acceleration of emulation circuits, and propose a systematic method to reduce the delay time of combinational circuits called 0&1 skip method. The proposed method is simpler compared to the existing method. We apply the 0&1 skip method for the acceleration of circuits on LUT-Based FPGA |
| Title | SAT Based Boolean Matching for Incompletely Specified Functions |
| Author | *Kuo-Hua Wang, Chung-Ming Chan (Fu Jen Catholic University, Taiwan) |
| Page | pp. 381 - 388 |
| Keyword | Boolean Matching, Boolean Satisfiability, Functional Symmetry, Signature |
| Abstract | Boolean matching is to check the equivalence of two functions under input permutation and input/output phase assignments. In this paper, we will transform the Boolean matching problem to the Boolean satisfiability problem. Based on this transformation approach, a SAT-based matching algorithm will be proposed. Our algorithm can not only handle completely specified functions but also incompletely specified functions. Moreover, two signatures exploiting functional symmetries will be provided to reduce the size of SAT instance and thus expedite the matching process. Experimental results on a set of benchmarking circuits show that our matching algorithm is indeed very effective and efficient to solve the Boolean matching problem. Compared with our prior work on Boolean matching [30], our SAT-based matching algorithm outperforms the old algorithm by several orders of magnitude for many large circuits. |
| Title | An Error Diagnosis Technique Based on Specifications with Don't Cares |
| Author | *Narumi Okada, Takayuki Iida, Toshiro Ishihara, Nobutaka Kuroki, Masahiro Numa (Kobe University, Japan) |
| Page | pp. 389 - 396 |
| Keyword | error diagnosis, don't cares, ECO, incremental synthesis, design error |
| Abstract | We present an error diagnosis technique for subcircuits based on specifications with don't cares. This technique combines two procedures for reducing the number of error candidates, screening for false error locations based on the specification defined with nine signal values for incorporating don’t cares, and and a Boolean function manipulation using characteristic function indicating don’t care input vectors for each primary output. Experimental results have shown that the proposed approach is effective to increase the number of solutions by incorporating don’t cares. |
| Title | An LUT-Based Error Diagnosis Technique Extended for Multiple Missing Line Errors Based on Iterative Diagnosis Procedure |
| Author | *Toshiro Ishihara, Ryosuke Arai, Narumi Okada, Nobutaka Kuroki, Masahiro Numa (Kobe University, Japan) |
| Page | pp. 397 - 404 |
| Keyword | incremental synthesis, error diagnosis, missing line error, iterative procedure |
| Abstract | In this paper, we propose an improved technique to rectify multiple logic design errors including multiple missing line errors in LUT-based combinational circuits. A conventional error diagnosis technique: EXL_SL can rectify only a single missing line error at a time. Our technique can rectify multiple missing line errors by employing iterative diagnosis procedure for subcircuits. Experimental results for ISCAS’85 benchmark circuits demonstrate that 79.0% of circuits including one to three missing line errors can be rectified successfully. |
| Title | Mixed-Abstraction Level Co-Simulation Environment for Dynamically Reconfigurable Processor Arrays |
| Author | *Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano (Keio University, Japan) |
| Page | pp. 405 - 411 |
| Keyword | Co-simulation, System level design, Dynamically reconfigurable processor, SystemC, Compiler |
| Abstract | In this paper, we present an automated design methodology and a design framework including System Generator, DRPA Generator, and DRPA Compiler for dynamically reconfigurable processor arrays (DRPAs). We have developed a System Generator which can generate a DRPA model written in SystemC and an interface wrapper using Verilog Procedural Interface (VPI) from application codes and a architecture description. We have integrated it to the tentative compiler based on COINS, and constructed a mixed-abstraction level co-simulation environment. |
| Title | Black-Diamond: a Retargetable Compiler using Graph with Configuration Bits for Dynamically Reconfigurable Architectures |
| Author | *Vasutan Tunbunheng, Hideharu Amano (Keio University, Japan) |
| Page | pp. 412 - 419 |
| Keyword | dynamically reconfigurable processor, retargetable compiler, placement and routing, multicontext |
| Abstract | For developing design envionment for various types of Dynamically Reconfigurable Processor Arrays (DRPAs), the GCI (Graph with Configuration Information) is proposed to represent configurable resource in the target dynamically reconfigurable architecture. The function unit, constant unit, register, and routing resource can be represented in the graph as well as the configuration information. The restriction in the hardware is added in the graph by using ``DisCounT'' port which is limited the possible configuration bits at the port controlled by the other ports. A prototype compiler called Black-Diamond with GCI is now available for three different DRPAs. It translates data-flow graph from C-like front-end description, applies placement and routing by using the GCI, and generates configuration data for each element of the DRPA in the form of multicasting. Implementation results of simple applications show that Black-Diamond can generate reasonable designs for three different architectures. |
| Title | A Reconfigurable Architecture with Special Functions for Shift Keying |
| Author | *Ayataka Kobayashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka University, Japan) |
| Page | pp. 420 - 426 |
| Keyword | Reconfigurable Architecture, shift keying |
| Abstract | This paper proposes a reconfigurable architecture for shift keying named RASK. RASK has a specialized ALU with specific functions and specialized processing elements for shift keying. Experimental results show that the proposed architecture achieves several shift keyings with small area compared to a reconfigurable architecture without specialized ALU. |
| Title | Topology Generation and Floorplanning for Low Power Application-Specific Network-on-Chips |
| Author | *Wan-Yu Lee, Iris Hui-Ru Jiang (Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Taiwan) |
| Page | pp. 427 - 432 |
| Keyword | Network-on-Chips, Low Power |
| Abstract | As the process advances into nanotechnology, the number of cores and the amount of communication on a chip are rapidly increasing. Using a micro-network, Network-on-Chip can overcome the communication inefficiency in the traditional shared bus communication architecture. The system performance of application-specific Network-on-Chips is mostly measured by power, timing, and area. Power and timing highly depend on how the network topology connects routers and cores and how many routers are used; area is simply determined by floorplanning. Unlike previous endeavors, we propose a new methodology to perform network topology generation before floorplanning. Moreover, our method can preserve the optimality of topology to floorplan. Our method not only minimizes power, satisfies timing and area constraints, but also guarantees deadlock free. Compared with previous work, the results show using the same number of routers, this approach can achieve competitive power consumption and have the above guarantees. |
| Title | Floorplan-Aware Design Methodology for Application-Specific Bus Matrix Systems |
| Author | *Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou (National Chiao Tung University, Taiwan) |
| Page | pp. 433 - 438 |
| Keyword | bus matrix, floorplan, multi-cycle communication, communication architecture |
| Abstract | The design of communication architectures becomes more and more important as modern systems require wider and wider communication bandwidth and the technology keeps the trend of miniaturization. Simultaneously considering the issues of hardware cost, system performance, and multi-cycle communication makes designing communication architectures even harder. In this paper, we propose a floorplan-aware design methodology for designing the bus matrix consisting of the minimum number of buses for a given system under the performance constraints and the assumption of multi-cycle communication. |
| Title | Low Power Object Oriented Synthesis for Electronic System-Level Design |
| Author | *Mehdi Kamal, Shaahin Hessabi (Sharif University of Technology, Iran) |
| Page | pp. 439 - 444 |
| Keyword | Object Oriented, Synthesis, Low Power, System Level |
| Abstract | Energy and power consumptions are becoming among the most important design factors due to portable device usage. Low power techniques are widely used in low level of design; similarly using this technique in system-level design is inevitable. In this paper, we use two techniques for low power synthesis of an object oriented (OO) system. We implement our proposed techniques in an OO synthesis tool, named ODYSSEY. We have added module-level clock gating and reduced the number of object's data accesses during synthesis and studied the power reduction of these two techniques. Clock gating part controls the clock during the system work and dynamically manages the power. Each class of design needs its data, so methods for must access a shared memory. Therefore, decreasing the access number reduces the power dissipation in interconnection network and improves the performance of system. we implemented this technique in algorithm-level. For evaluating the proposed techniques, we have considered JpegDecoder, JpegEncoder and Genetic Algorithm benchmarks. Experiments show that the clock gating technique reduces power dissipation about 45%. Decreasing the number of object's data accesses reduces power and improves the performance of system. |