The 14th Workshop on Synthesis And System Integration of Mixed Information technologies
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Monday, October 15, 2007


Opening 9:10 - 9:20
K (Conference Hall (2F)) Keynote Speech 9:20 - 10:20
R1 (Conference Hall (2F) & Poster Room (2F)) Design Experience I 10:20 - 12:05
Lunch 12:05 - 13:25
I1 (Conference Hall (2F)) Invited Talk I 13:25 - 14:10
R2 (Conference Hall (2F) & Poster Room (2F)) FPGA, Place & Route 14:10 - 15:50
I2 (Conference Hall (2F)) Invited Talk II 15:50 - 16:35
R3 (Conference Hall (2F) & Poster Room (2F)) Design Methodology for Nanometer Era 16:35 - 18:15
Banquet 18:30 - 20:30

Tuesday, October 16, 2007


I3 (Conference Hall (2F)) Invited Talk III 9:00 - 9:45
R4 (Conference Hall (2F) & Poster Room (2F)) System Level Design & Logic Synthesis 9:45 - 11:30
I4 (Conference Hall (2F)) Invited Talk IV 11:30 - 12:15
Lunch 12:15 - 13:30
I5 (Conference Hall (2F)) Invited Talk V 13:30 - 14:15
R5 (Conference Hall (2F) & Poster Room (2F)) Design Verification & Design Experience II 14:15 - 16:00
D (Conference Hall (2F)) Panel Discussion 16:00 - 17:30
Closing 17:30 - 17:40

List of Papers

Remark: The presenter of each paper is marked with "*".

Monday, October 15, 2007

Keynote Speech
Time: 9:20 - 10:20 Monday, October 15, 2007
Location: Conference Hall (2F)
Chair: Shinji Kimura (Waseda Univ., Japan)

K-1 (Time: 9:20 - 10:20)

Title	Future Design Paradigms: Technologies, Circuits and Architectures
Author	*Giovanni De Micheli (CSI, EPFL, Switzerland)
Page	p. 3
Detailed information (abstract, keywords, etc)

Design Experience I
Time: 10:20 - 12:05 Monday, October 15, 2007
Location: Conference Hall (2F) & Poster Room (2F)
Chairs: Chun-Yao Wang (National Tsing Hua Univ., Taiwan), Tohru Ishihara (Kyushu Univ., Japan)

R1-1 (Time: 10:20 - 10:22)

Title	Power-Conscious Synthesis of Parallel Prefix Adders under Bitwise Timing Constraints
Author	*Taeko Matsunaga, Shinji Kimura (Waseda Univ., Japan), Yusuke Matsunaga (Kyushu Univ., Japan)
Page	pp. 7 - 14
Detailed information (abstract, keywords, etc)

R1-2 (Time: 10:22 - 10:24)

Title	Design of a Combined Circuit for Multiplication and Inversion in GF(2^m)
Author	*Katsuki Kobayashi, Naofumi Takagi (Nagoya Univ., Japan)
Page	pp. 15 - 20
Detailed information (abstract, keywords, etc)

R1-3 (Time: 10:24 - 10:26)

Title	Associative Memory Design Realizing Reference-Pattern Recognition and Learning based on Short/Long-Term Storage Concept
Author	*Shogo Sakakibara, Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi , Hans Jüergen Mattausch, Tetsushi Koide (Hiroshima Univ., Japan)
Page	pp. 21 - 25
Detailed information (abstract, keywords, etc)

R1-4 (Time: 10:26 - 10:28)

Title	Acceleration of Advanced Encryption Standard (AES) Processing on a CAM Enhanced Super Parallel SIMD Processor
Author	*Masaharu Tagami, Masakatsu Ishizaki, Takeshi Kumaki, Yutaka Kono, Tetsushi Koide, Hans Jüergen Mattausch (Hiroshima Univ., Japan), Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas Technology Corp., Japan)
Page	pp. 26 - 31
Detailed information (abstract, keywords, etc)

R1-5 (Time: 10:28 - 10:30)

Title	Hardware Realization of Two-Stage Pattern Matching System using Fully-Parallel Associative Memories
Author	*Md. Anwarul Abedin, Yuki Tanaka, Shogo Sakakibara, Ali Ahmadi , Tetsushi Koide, Hans Jüergen Mattausch (Hiroshima Univ., Japan)
Page	pp. 32 - 37
Detailed information (abstract, keywords, etc)

R1-6 (Time: 10:30 - 10:32)

Title	A Fast Differential-Amplifier-Based Winner-Search circuit for Fully Parallel Associative Memories
Author	*Yuki Tanaka, Md. Anwarul Abedin, Shogo Sakakibara, Tetsushi Koide, Hans Jüergen Mattausch (Hiroshima Univ., Japan)
Page	pp. 38 - 41
Detailed information (abstract, keywords, etc)

R1-7 (Time: 10:32 - 10:34)

Title	Reducing the Dynamic Energy Consumption in the Multi-Layer Memory of Embedded Multimedia Processing Systems
Author	*Ilie I. Luican (Univ. of Illinois, Chicago, United States), Hongwei Zhu (ARM, Inc., United States), Florin Balasa (Southern Utah Univ., United States), Dhiraj K. Pradhan (Univ. of Bristol, Great Britain)
Page	pp. 42 - 48
Detailed information (abstract, keywords, etc)

R1-8 (Time: 10:34 - 10:36)

Title	An Output Probability Computation Circuit Design for Real Time Speech Recognition
Author	*Joe Hashimoto, Akihiko Eguchi, Makoto Saituji (Kinki Univ., Japan), Akihisa Yamada (Sharp Corp., Japan), Takashi Kambe (Kinki Univ., Japan)
Page	pp. 49 - 55
Detailed information (abstract, keywords, etc)

R1-9 (Time: 10:36 - 10:38)

Title	A Hybrid Memory Architecture for Low Power Embedded System Design
Author	*Tadayuki Matsumura, Yuriko Ishitobi, Tohru Ishihara, Maziar Goudarzi, Hiroto Yasuura (Kyushu Univ., Japan)
Page	pp. 56 - 62
Detailed information (abstract, keywords, etc)

R1-10 (Time: 10:38 - 10:40)

Title	An Accurate and Efficient Lane Recognition Algorithm for Automotive Active Safety System
Author	*Yusuke Watanabe, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 63 - 68
Detailed information (abstract, keywords, etc)

R1-11 (Time: 10:40 - 10:42)

Title	Performance Evaluation of Region-Growing Image Segmentation Using Two-Dimensional Image-Block Scanning
Author	*Keita Okazaki, Kazutoshi Awane, Kosuke Yamaoka, Tetsushi Koide, Hans Jüergen Mattausch (Hiroshima Univ., Japan)
Page	pp. 69 - 73
Detailed information (abstract, keywords, etc)

R1-12 (Time: 10:42 - 10:44)

Title	An Effective Parallel Coding Architecture Utilizing Characteristics of Multimedia Application
Author	*Takeshi Kumaki, Masakatsu Ishizaki, Masaharu Tagami, Tetsushi Koide, Hans Jüergen Mattausch (Hiroshima Univ., Japan)
Page	pp. 74 - 80
Detailed information (abstract, keywords, etc)

R1-13 (Time: 10:44 - 10:46)

Title	VLSI Architecture for Real-time Retinex Video Image Enhancement
Author	*Kazuyuki Takahashi, Yoshihiro Nozato (Osaka Univ., Japan), Hiroyuki Okuhata (Synthesis Corp., Japan), Takao Onoye (Osaka Univ., Japan)
Page	pp. 81 - 86
Detailed information (abstract, keywords, etc)

R1-14 (Time: 10:46 - 10:48)

Title	ΣΔ-Modulator with High Nearby Interferers Suppression by Transmission Zeroes
Author	*Takashi Moue, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Page	pp. 87 - 90
Detailed information (abstract, keywords, etc)

R1-15 (Time: 10:48 - 10:50)

Title	The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time
Author	Masaya Miyahara, *Hiroki Endou, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Page	pp. 91 - 96
Detailed information (abstract, keywords, etc)

R1-16 (Time: 10:50 - 10:52)

Title	A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique
Author	*Shuaiqi Wang (Waseda Univ., Japan), Fule Li (Tsinghua Univ., China), Yasuaki Inoue (Waseda Univ., Japan)
Page	pp. 97 - 103
Detailed information (abstract, keywords, etc)

Invited Talk I
Time: 13:25 - 14:10 Monday, October 15, 2007
Location: Conference Hall (2F)
Chair: Takao Onoye (Osaka Univ., Japan)

I1-1 (Time: 13:25 - 14:10)

Title	Reconfigurable Architecture: Challenges and Impacts for Multimedia
Author	Chung-Jr Lian, You Ming Tsao, *Liang-Gee Chen (National Taiwan Univ., Taiwan)
Page	pp. 107 - 111
Detailed information (abstract, keywords, etc)

FPGA, Place & Route
Time: 14:10 - 15:50 Monday, October 15, 2007
Location: Conference Hall (2F) & Poster Room (2F)
Chairs: Hung-Ming Chen (National Chiao Tung Univ., Taiwan), Yasuhiro Takashima (Univ. of Kitakyushu, Japan)

R2-1 (Time: 14:10 - 14:12)

Title	A BCH Decode Accelerator for Application Specific Processors
Author	*Kazuhito Ito (Saitama Univ., Japan)
Page	pp. 115 - 121
Detailed information (abstract, keywords, etc)

R2-2 (Time: 14:12 - 14:14)

Title	Design and FPGA Implementation of a High-Speed String Matching Engine
Author	*Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ., Japan)
Page	pp. 122 - 129
Detailed information (abstract, keywords, etc)

R2-3 (Time: 14:14 - 14:16)

Title	Speed Improvement of AES Encryption using Hardware Acclererators Synthesized by C Compatible Architecture Prototyper (CCAP)
Author	*Hiroyuki Kanbara (ASTEM RI, Japan), Takayuki Nakatani, Naoto Umehara (Ritsumeikan Univ., Japan), Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Hiroyuki Tomiyama (Nagoya Univ., Japan)
Page	pp. 130 - 134
Detailed information (abstract, keywords, etc)

R2-4 (Time: 14:16 - 14:18)

Title	A Hybrid Logic Simulator Using LUT Cascade Emulators
Author	*Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech., Japan)
Page	pp. 135 - 141
Detailed information (abstract, keywords, etc)

R2-5 (Time: 14:18 - 14:20)

Title	Statistical Estimation Method for Verification Coverage Using FPGA-based Emulators
Author	*Kohei Hosokawa, Yuichi Nakamura (NEC, Japan), Baku Haraguchi (NEC Micro Systems, Japan)
Page	pp. 142 - 146
Detailed information (abstract, keywords, etc)

R2-6 (Time: 14:20 - 14:22)

Title	Blockage-Aware Routing Tree Construction with Concurrent Buffer and Flip-Flop Insertion
Author	Shu-Yun Chen (Realtek Semiconductor Corp., Taiwan), *Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 147 - 154
Detailed information (abstract, keywords, etc)

R2-7 (Time: 14:22 - 14:24)

Title	Low-Power Clock Tree Synthesis by Low-Swing Techniques
Author	Yun-Ta Lin (SpringSoft, Inc., Taiwan), *Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Page	pp. 155 - 160
Detailed information (abstract, keywords, etc)

R2-8 (Time: 14:24 - 14:26)

Title	Post-Silicon Clock-timing Tuning Based on Statistical Estimation
Author	*Yuko Hashizume, Yasuhiro Takashima (Univ. of Kitakyushu, Japan), Yuichi Nakamura (NEC Corp., Japan)
Page	pp. 161 - 165
Detailed information (abstract, keywords, etc)

R2-9 (Time: 14:26 - 14:28)

Title	Speed Enhancement Technique for the Post-fabrication Clock-timing Adjustment of Digital LSIs
Author	*Tatsuya Susa (Toho Univ., Japan), Masahiro Murakawa, Eiichi Takahashi (AIST, Japan), Tatsumi Furuya (Toho Univ., Japan), Tetsuya Higuchi (AIST, Japan), Shinji Furuichi, Yoshitaka Ueda, Atsushi Wada (Sanyo Electric Co., Ltd, Japan)
Page	pp. 166 - 173
Detailed information (abstract, keywords, etc)

R2-10 (Time: 14:28 - 14:30)

Title	Repairs for Voltage Drop and Noise Violation in Late Design Stages
Author	Shih-Tsung Huang (AnaGlobe Technology, Taiwan), *Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Page	pp. 174 - 178
Detailed information (abstract, keywords, etc)

R2-11 (Time: 14:30 - 14:32)

Title	Estimation of Yield Enhancement by Critical Path Reconfiguration Utilizing Random Variations on Deep-submicron FPGAs
Author	*Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 179 - 183
Detailed information (abstract, keywords, etc)

R2-12 (Time: 14:32 - 14:34)

Title	A Mixed Integer Linear Programming Based Approach for Post-Routing Redundant Via Insertion
Author	Kuang-Yao Lee, *Ting-Chi Wang (National Tsing Hua Univ., Taiwan), Kai-Yuan Chao (Intel Corp., United States)
Page	pp. 184 - 191
Detailed information (abstract, keywords, etc)

R2-13 (Time: 14:34 - 14:36)

Title	Fast Monotonic Via Assignment Excluding Mold Gates for 2-Layer Ball Grid Array Packages
Author	*Yoichi Tomioka, Atsushi Takahashi (Tokyo Inst. of Tech., Japan)
Page	pp. 192 - 197
Detailed information (abstract, keywords, etc)

R2-14 (Time: 14:36 - 14:38)

Title	An I/O Planning Method for Three-Dimensional Integrated Circuits
Author	*Chao-Hung Lu (National Central Univ., Taiwan), Hung-Ming Chen (National Chiao Tung Univ., Taiwan), Chien-Nan Jimmy Liu, Wen-Yu Shih (National Central Univ., Taiwan)
Page	pp. 198 - 202
Detailed information (abstract, keywords, etc)

R2-15 (Time: 14:38 - 14:40)

Title	Non-Slicing Floorplanning-Based Crosstalk Reduction on Gridless Track Assignment
Author	*Wen-Nai Cheng, Yu-Ning Chang, Yih-Lang Li (National Chiao-Tung Univ., Taiwan)
Page	pp. 203 - 207
Detailed information (abstract, keywords, etc)

R2-16 (Time: 14:40 - 14:42)

Title	Fujimaki-Takahashi Squeeze : Linear Time Construction of Constraint Graphs of a Floorplan for a Given Permutation
Author	*Ryo Fujimaki, Toshihiko Takahashi (Niigata Univ., Japan)
Page	pp. 208 - 213
Detailed information (abstract, keywords, etc)

R2-17 (Time: 14:42 - 14:44)

Title	Placement with Symmetry Constraints for Analog IC Layout Design based on Tree Representation
Author	*Natsumi Hirakawa, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan)
Page	pp. 214 - 221
Detailed information (abstract, keywords, etc)

Invited Talk II
Time: 15:50 - 16:35 Monday, October 15, 2007
Location: Conference Hall (2F)
Chair: Yusuke Matsunaga (Kyushu Univ., Japan)

I2-1 (Time: 15:50 - 16:35)

Title	Why Study Quantum Circuits and What They Are Good For
Author	*Igor Markov (Univ. of Michigan, United States)
Page	pp. 225 - 230
Detailed information (abstract, keywords, etc)

Design Methodology for Nanometer Era
Time: 16:35 - 18:15 Monday, October 15, 2007
Location: Conference Hall (2F) & Poster Room (2F)
Chairs: Ting-Chi Wang (National Tsing Hua Univ., Taiwan), Youhua Shi (Waseda Univ., Japan)

R3-1 (Time: 16:35 - 16:45)

Title	A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability
Author	*Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ., Japan)
Page	pp. 233 - 237
Detailed information (abstract, keywords, etc)

R3-2 (Time: 16:45 - 16:47)

Title	Simulations of Flicker Noise in SiGe HMOS: Body Bias Dependence
Author	*C.-Y. Chen, Y. Liu, R. W. Dutton (Stanford Univ., United States), J. Sato-Iwanaga, A. Inoue, H. Sorada (Matsushita Electric Industrial Co., Ltd, Japan)
Page	pp. 238 - 241
Detailed information (abstract, keywords, etc)

R3-3 (Time: 16:47 - 16:49)

Title	Active Body-Biasing Control on PD-SOI for Dual Supply Voltage Scheme
Author	*Yosuke Torii, Kenji Hamada, Kayoko Seto, Masaaki Iijima, Masahiro Numa (Kobe Univ., Japan), Akira Tada, Takashi Ipposhi (Renesas Technology Corp., Japan)
Page	pp. 242 - 245
Detailed information (abstract, keywords, etc)

R3-4 (Time: 16:49 - 16:51)

Title	A Look-Ahead Active Body-Biasing Scheme for SOI-SRAM with Dynamic V_DDM Control
Author	*Kayoko Seto, Yosuke Torii, Masaaki Iijima, Masahiro Numa (Kobe Univ., Japan), Akira Tada, Takashi Ipposhi (Renesas Technology Corp., Japan)
Page	pp. 246 - 249
Detailed information (abstract, keywords, etc)

R3-5 (Time: 16:51 - 16:53)

Title	A Study on Variation-Component Decomposition using Polynomial Smoothing Function
Author	*Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu (Tokyo Inst. of Tech., Japan)
Page	pp. 250 - 255
Detailed information (abstract, keywords, etc)

R3-6 (Time: 16:53 - 16:55)

Title	Effect of Dummy Fills on High Frequency Characteristics of Spiral Inductor
Author	*Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 256 - 260
Detailed information (abstract, keywords, etc)

R3-7 (Time: 16:55 - 16:57)

Title	Static-Noise-Margin Analysis of Major SRAM-Cell Types Including Production Variations for a 90nm CMOS Process
Author	*Shinya Izumi, Koh Johguchi, Hans Jüergen Mattausch, Tetsushi Koide (Hiroshima Univ., Japan)
Page	pp. 261 - 265
Detailed information (abstract, keywords, etc)

R3-8 (Time: 16:57 - 16:59)

Title	Active Mode Leakage Power Reduction Based on the Controlling Value of Logic Gates
Author	*Lei Chen, Shinji Kimura (Waseda Univ., Japan)
Page	pp. 266 - 271
Detailed information (abstract, keywords, etc)

R3-9 (Time: 16:59 - 17:01)

Title	Structural Robustness of Datapaths against Delay-Variation
Author	*Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST, Japan)
Page	pp. 272 - 279
Detailed information (abstract, keywords, etc)

R3-10 (Time: 17:01 - 17:03)

Title	Critical Issues Regarding A Variation Resilient Flip-Flop
Author	Toshinori Sato (Kyushu Univ., Japan), *Yuji Kunitake (Kyushu Inst. of Tech., Japan)
Page	pp. 280 - 286
Detailed information (abstract, keywords, etc)

R3-11 (Time: 17:03 - 17:05)

Title	A Case Study of Multi-processor Design with Asynchronous Interconnect using Synchronous Design Tools
Author	*Katsunori Tanaka, Yuichi Nakamura, Atsushi Atarashi (NEC Corp., Japan)
Page	pp. 287 - 293
Detailed information (abstract, keywords, etc)

R3-12 (Time: 17:05 - 17:07)

Title	An Asynchronous Single-precision Floating-point Divider and its Implementation on FPGA
Author	*Masayuki Hiromoto, Shin'ichi Kouyama, Hiroyuki Ochi (Kyoto Univ., Japan), Yukihiro Nakamura (Ritsumeikan Univ., Japan)
Page	pp. 294 - 301
Detailed information (abstract, keywords, etc)

R3-13 (Time: 17:07 - 17:09)

Title	Full-Chip Thermal Analysis via Generalized Integral Transforms
Author	*Pei-Yu Haung, Chih-Kang Lin, Yu-Min Lee (National Chiao Tung Univ., Taiwan)
Page	pp. 302 - 309
Detailed information (abstract, keywords, etc)

R3-14 (Time: 17:09 - 17:11)

Title	A Power Grid Optimization Algorithm by Direct Observation of Timing Error Risk Reduction
Author	*Makoto Terao, Kenji Kusano, Yoshiyuki Kawakami, Masahiro Fukui (Ritsumeikan Univ., Japan), Shuji Tsukiyama (Chuo Univ., Japan)
Page	pp. 310 - 315
Detailed information (abstract, keywords, etc)

R3-15 (Time: 17:11 - 17:13)

Title	A High-level Power Grid Optimization Algorithm by Direct Observation of Manufacturing Cost Reduction
Author	*Takayuki Hayashi, Hironobu Ishijima, Yoshiyuki Kawakami, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 316 - 321
Detailed information (abstract, keywords, etc)

R3-16 (Time: 17:13 - 17:15)

Title	An Evaluation of Circuit Simulation Algorithms for Hardware Implementation
Author	*Taiki Hashizume, Hironobu Ishijima, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 322 - 327
Detailed information (abstract, keywords, etc)

Tuesday, October 16, 2007

Invited Talk III
Time: 9:00 - 9:45 Tuesday, October 16, 2007
Location: Conference Hall (2F)
Chair: Masahiro Fujita (Univ. of Tokyo, Japan)

I3-1 (Time: 9:00 - 9:45)

Title	Dynamic Analysis of Concurrent Systems
Author	*Gul Agha (Univ. of Illinois, Urbana-Champaign, United States)
Page	pp. 331 - 334
Detailed information (abstract, keywords, etc)

System Level Design & Logic Synthesis
Time: 9:45 - 11:30 Tuesday, October 16, 2007
Location: Conference Hall (2F) & Poster Room (2F)
Chairs: Bernard Courtois (CMP, France), Yukio Mitsuyama (Osaka Univ., Japan)

R4-1 (Time: 9:45 - 9:47)

Title	An Object-Oriented Circuit Design Method and Its Evaluation
Author	*Seigo Masuoka, Hiroyuki Terai, Manabu Koyama (Kinki Univ., Japan), Kazuhiko Nakahara (Spansion Japan Corp., Japan), Akihisa Yamada (Sharp Corp., Japan), Takashi Kambe (Kinki Univ., Japan)
Page	pp. 337 - 342
Detailed information (abstract, keywords, etc)

R4-2 (Time: 9:47 - 9:49)

Title	Object Oriented Design and Synthesis of Communication in Hardware-/Software Systems with OSSS
Author	*Kim Grüttner, Cornelia Grabbe, Frank Oppenheimer (OFFIS - Institute for Information Technology, Germany), Wolfgang Nebel (Carl v. Ossietzky Univ. Oldenburg, Germany)
Page	pp. 343 - 350
Detailed information (abstract, keywords, etc)

R4-3 (Time: 9:49 - 9:51)

Title	A Data Arrangement Method for Block Floating Point Systems
Author	*Takashi Hamabe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Page	pp. 351 - 356
Detailed information (abstract, keywords, etc)

R4-4 (Time: 9:51 - 9:53)

Title	Calling Software Functions from Hardware Functions in High-Level Synthesizer CCAP
Author	*Masanari Nishimura, Nagisa Ishiura, Yoshiyuki Ishimori (Kwansei Gakuin Univ., Japan), Hiroyuki Kanbara (ASTEM RI, Japan), Hiroyuki Tomiyama (Nagoya Univ., Japan)
Page	pp. 357 - 360
Detailed information (abstract, keywords, etc)

R4-5 (Time: 9:53 - 9:55)

Title	Performance-Aware Communication Architecture Synthesis
Author	*Alexander Viehl, Oliver Bringmann (FZI Forschungszentrum Informatik, Germany), Wolfgang Rosenstiel (Univ. Tübingen, Germany)
Page	pp. 361 - 368
Detailed information (abstract, keywords, etc)

R4-6 (Time: 9:55 - 9:57)

Title	A Network Processor Synthesis System for Task-Chaining Network Applications
Author	*Youhua Shi, Keishi Nakayama, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ., Japan)
Page	pp. 369 - 374
Detailed information (abstract, keywords, etc)

R4-7 (Time: 9:57 - 9:59)

Title	Resynthesis Method for Circuit Acceleration on LUT-based FPGA
Author	*Weijie Xing (Waseda Univ., Japan), Takashi Horiyama (Saitama Univ., Japan), Shunichi Kuromaru, Tomoo Kimura (Matsushita Electric Industrial Co., Ltd, Japan), Shinji Kimura (Waseda Univ., Japan)
Page	pp. 375 - 380
Detailed information (abstract, keywords, etc)

R4-8 (Time: 9:59 - 10:01)

Title	SAT Based Boolean Matching for Incompletely Specified Functions
Author	*Kuo-Hua Wang, Chung-Ming Chan (Fu Jen Catholic Univ., Taiwan)
Page	pp. 381 - 388
Detailed information (abstract, keywords, etc)

R4-9 (Time: 10:01 - 10:03)

Title	An Error Diagnosis Technique Based on Specifications with Don't Cares
Author	*Narumi Okada, Takayuki Iida, Toshiro Ishihara, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 389 - 396
Detailed information (abstract, keywords, etc)

R4-10 (Time: 10:03 - 10:05)

Title	An LUT-Based Error Diagnosis Technique Extended for Multiple Missing Line Errors Based on Iterative Diagnosis Procedure
Author	*Toshiro Ishihara, Ryosuke Arai, Narumi Okada, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 397 - 404
Detailed information (abstract, keywords, etc)

R4-11 (Time: 10:05 - 10:07)

Title	Mixed-Abstraction Level Co-Simulation Environment for Dynamically Reconfigurable Processor Arrays
Author	*Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano (Keio Univ., Japan)
Page	pp. 405 - 411
Detailed information (abstract, keywords, etc)

R4-12 (Time: 10:07 - 10:09)

Title	Black-Diamond: a Retargetable Compiler using Graph with Configuration Bits for Dynamically Reconfigurable Architectures
Author	*Vasutan Tunbunheng, Hideharu Amano (Keio Univ., Japan)
Page	pp. 412 - 419
Detailed information (abstract, keywords, etc)

R4-13 (Time: 10:09 - 10:11)

Title	A Reconfigurable Architecture with Special Functions for Shift Keying
Author	*Ayataka Kobayashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Page	pp. 420 - 426
Detailed information (abstract, keywords, etc)

R4-14 (Time: 10:11 - 10:13)

Title	Topology Generation and Floorplanning for Low Power Application-Specific Network-on-Chips
Author	*Wan-Yu Lee, Iris Hui-Ru Jiang (National Chiao Tung Univ., Taiwan)
Page	pp. 427 - 432
Detailed information (abstract, keywords, etc)

R4-15 (Time: 10:13 - 10:15)

Title	Floorplan-Aware Design Methodology for Application-Specific Bus Matrix Systems
Author	*Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou (National Chiao Tung Univ., Taiwan)
Page	pp. 433 - 438
Detailed information (abstract, keywords, etc)

R4-16 (Time: 10:15 - 10:17)

Title	Low Power Object Oriented Synthesis for Electronic System-Level Design
Author	*Mehdi Kamal, Shaahin Hessabi (Sharif Univ. of Tech., Iran)
Page	pp. 439 - 444
Detailed information (abstract, keywords, etc)

Invited Talk IV
Time: 11:30 - 12:15 Tuesday, October 16, 2007
Location: Conference Hall (2F)
Chair: Hidetoshi Onodera (Kyoto Univ., Japan)

I4-1 (Time: 11:30 - 12:15)

Title	Statistical Techniques to Combat Variability and Achieve Robust Design
Author	*Chandu Visweswariah (IBM, United States)
Page	p. 447
Detailed information (abstract, keywords, etc)

Invited Talk V
Time: 13:30 - 14:15 Tuesday, October 16, 2007
Location: Conference Hall (2F)
Chair: Shin'ichi Wakabayashi (Hiroshima City Univ., Japan)

I5-1 (Time: 13:30 - 14:15)

Title	Current Status of LSI Micro-Fabrication and Future Prospect for 3D System and Design Integration
Author	*Kazuya Okamoto (Osaka Univ., Japan)
Page	pp. 451 - 457
Detailed information (abstract, keywords, etc)

Design Verification & Design Experience II
Time: 14:15 - 16:00 Tuesday, October 16, 2007
Location: Conference Hall (2F) & Poster Room (2F)
Chairs: Chien-Nan Liu (National Central Univ., Taiwan), Qiang Zhu (Cadence Design Systems, Japan)

R5-1 (Time: 14:15 - 14:17)

Title	Formal Representation and Verification of Arithmetic Circuits Using Symbolic Computer Algebra
Author	*Yuki Watanabe, Naofumi Homma, Takafumi Aoki (Tohoku Univ., Japan), Tatsuo Higuchi (Tohoku Inst. of Tech., Japan)
Page	pp. 461 - 468
Detailed information (abstract, keywords, etc)

R5-2 (Time: 14:17 - 14:19)

Title	Range Equivalent Circuit Minimization
Author	*Yung-Chih Chen, Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 469 - 476
Detailed information (abstract, keywords, etc)

R5-3 (Time: 14:19 - 14:21)

Title	Predictive Test Strategy for CMOS RF Mixers
Author	*Kay Suenaga, Rodrigo Picos, Sebastia Bota, Miquel Roca, Eugeni Isern, Eugeni Garcia-Moreno (Univ. of Balearic Islands, Spain)
Page	pp. 477 - 483
Detailed information (abstract, keywords, etc)

R5-4 (Time: 14:21 - 14:23)

Title	Unifying AMBA based Verification Environment at SystemC / RTL / FPGA Levels: Using 3D Graphics SoC As an Example
Author	*Wei-Sheng Huang, Ruei-Ting Gu, Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)
Page	pp. 484 - 487
Detailed information (abstract, keywords, etc)

R5-5 (Time: 14:23 - 14:25)

Title	Hardware/Software Covalidation with FPGA and RTOS Model
Author	*Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ., Japan)
Page	pp. 488 - 494
Detailed information (abstract, keywords, etc)

R5-6 (Time: 14:25 - 14:27)

Title	Pipeline-Aware Instruction-Level Power Analysis for VLIW DSP Core
Author	Wen-Tsan Hsieh, Hsin-Ying Liao, *Chien-Nan Jimmy Liu (National Central Univ., Taiwan), Shu-Yu Cheng, Ji-Jan Chen (SOC Technology Center of Industrial Technological Research Institute, Taiwan)
Page	pp. 495 - 499
Detailed information (abstract, keywords, etc)

R5-7 (Time: 14:27 - 14:29)

Title	Automatic Generation of Custom Interface Transactors for Verification Environments
Author	*Rafael K. Morizawa, Hiroaki Iwashita, Koichiro Takayama (Fujitsu Laboratories, LTD., Japan)
Page	pp. 500 - 506
Detailed information (abstract, keywords, etc)

R5-8 (Time: 14:29 - 14:31)

Title	Analog Simulation Meets Digital Verification- A Formal Assertion Approach for Mixed-Signal Verification
Author	*Alexander Jesser, Lars Hedrich (Univ. of Frankfurt a.M., Germany), Stefan Laemmermann, Roland Weiss, Juergen Ruf, Thomas Kropf, Wolfgang Rosenstiel (Univ. of Tuebingen, Germany), Alexander Pacholik, Wolfgang Fengler (Technical Univ. of Ilmenau, Germany)
Page	pp. 507 - 514
Detailed information (abstract, keywords, etc)

R5-9 (Time: 14:31 - 14:33)

Title	Encoding Assertions with Dynamic Local Variables for Bounded Property Checking
Author	*Sho Takeuchi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ., Japan)
Page	pp. 515 - 521
Detailed information (abstract, keywords, etc)

R5-10 (Time: 14:33 - 14:35)

Title	Evaluation of All-Digital PLL by Using Clock-Period Comparator
Author	*Yukinobu Makihara, Masayuki Ikebe, Eiichi Sano (Hokkaido Univ., Japan)
Page	pp. 522 - 528
Detailed information (abstract, keywords, etc)

R5-11 (Time: 14:35 - 14:37)

Title	A Lateral Unified-CBiCMOS Buffer Circuit for Driving 5-nF Maximum Load Capacitance per CCD Clock
Author	*Masatoshi Kobayashi, Takashi Hamahata, Toshiro Akino (Kinki Univ., Japan), Kenji Nishi (Kinki Univ. Technology College, Japan), Cuong Vo Le, Kohsei Takehara, T. Goji Etoh (Kinki Univ., Japan)
Page	pp. 529 - 535
Detailed information (abstract, keywords, etc)

R5-12 (Time: 14:37 - 14:39)

Title	A CMOS Transconductor with Rail-to-Rail Input Stage under 1.8-V Supply Voltage
Author	*Tien-Yu Lo, Cheng-Sheng Kao, Wen-Hung Hsieh, Chung-Chih Hung (National Chiao Tung Univ., Taiwan)
Page	pp. 536 - 539
Detailed information (abstract, keywords, etc)

R5-13 (Time: 14:39 - 14:41)

Title	Charge Recycling between Divided Blocks in MTCMOS Circuits
Author	*Akira Tada, Hiromi Notani, Genichi Tanaka, Takashi Ipposhi (Renesas Technology Corp., Japan), Masaaki Iijima, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 540 - 544
Detailed information (abstract, keywords, etc)

R5-14 (Time: 14:41 - 14:43)

Title	CoDaMa: An XML-based Framework to Manipulate Control Data Flow Graphs
Author	*Shunitsu Kohara, Shi Youhua, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ., Japan)
Page	pp. 545 - 549
Detailed information (abstract, keywords, etc)

Panel Discussion
Time: 16:00 - 17:30 Tuesday, October 16, 2007
Location: Conference Hall (2F)

D-1 (Time: 16:00 - 17:30)

Title	The End of Traditional CMOS
Author	*Moderator: Raul Camposano (Xoomsys, United States), Panelists: Gul Agha (Univ. of Illinois, Urbana-Champaign, United States), Yasuhiko Hagihara (NEC Corp., Japan), Igor Markov (Univ. of Michigan, United States), Chandu Visweswariah (IBM, United States)
Page	p. 553
Detailed information (abstract, keywords, etc)

The 14th Workshop on Synthesis And System Integration of Mixed Information technologies Technical Program

Session Schedule

List of Papers

The 14th Workshop on Synthesis And System Integration of Mixed Information technologies
Technical Program