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The 16th Workshop on Synthesis And System Integration of Mixed Information Technologies

Paper Session II: Logic and Physical Design (I)
Time: 14:15 - 16:00 Monday, October 18, 2010
Location: Ballroom
Chairs: Takashi Horiyama (Saitama Univ., Japan), Hui-Ru Iris Jiang (National Chiao Tung Univ., Taiwan)

R2-1 (Time: 14:15 - 14:17)
TitleStable-LSE based Analytical Placement with Overlap Removable Length
Author*Masatomo Kuwano, Yasuhiro Takashima (Univ. of Kitakyushu, Japan)
Pagepp. 115 - 120
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R2-2 (Time: 14:17 - 14:19)
TitleMetal Balance Based Clock Construction to Minimize Process Variation Effect
Author*Zhi-Wei Chen (Inst. of Information Industry, Taiwan), Hung-Ming Chen, Ren-Jie Lee, Chun-Kai Wang (National Chiao Tung Univ., Taiwan)
Pagepp. 121 - 125
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R2-3 (Time: 14:19 - 14:21)
TitleCircuit Performance Degradation on FPGAs Considering NBTI and Process Variations
Author*Michitarou Yabuuchi, Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan)
Pagepp. 126 - 129
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R2-4 (Time: 14:21 - 14:23)
TitleRover: Routing on Via-Configurable Fabrics for Standard-Cell-Like Structured ASICs
Author*Liang-Chi Lai, Hsih-Han Chang, Rung-Bin Lin (Yuan Ze Univ., Taiwan)
Pagepp. 130 - 135
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R2-5 (Time: 14:23 - 14:25)
TitleA Physical-Location-Aware Fault Redistribution for Maximum IR-Drop Reduction
Author*Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang (National Tsing Hua Univ., Taiwan)
Pagepp. 136 - 141
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R2-6 (Time: 14:25 - 14:27)
TitleRedundant Via Insertion under Timing Constraints
Author*Chi-Wen Pan, Yu-Min Lee (National Chiao Tung Univ., Taiwan)
Pagepp. 142 - 147
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R2-7 (Time: 14:27 - 14:29)
TitleOptimal Wiring Topology for Electromigration Avoidance
AuthorIris Hui-Ru Jiang (National Chiao Tung Univ., Taiwan), Hua-Yu Chang (National Taiwan Univ., Taiwan), *Chih-Long Chang (National Chiao Tung Univ., Taiwan)
Pagepp. 148 - 153
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R2-8 (Time: 14:29 - 14:31)
TitleIterative 3D Partitioning for Through-Silicon Via Minimization
Author*Ya-Shih Huang, Yang-Hsiang Liu, Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Pagepp. 154 - 159
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R2-9 (Time: 14:31 - 14:33)
TitleA Novel Zone-Based ILP Track Routing
Author*Ke-Ren Dai, Yi-Chun Lin, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Pagepp. 160 - 165
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R2-10 (Time: 14:33 - 14:35)
Title3D-AADI: An Adaptive and Integrable Thermal Simulator According to ADI Concept for 3D IC Physical Design Flow
Author*Sophie Ting-Jung Li, Yu-Min Lee (National Chiao Tung Univ., Taiwan)
Pagepp. 166 - 171
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R2-11 (Time: 14:35 - 14:37)
TitleAn ILP-based Diagnosis Framework For Multiple Open-Segment Defects
AuthorChen-Yuan Kao, Chien-Hui Liao, *Charles Hung-Ping Wen (National Chiao Tung Univ., Taiwan)
Pagepp. 172 - 177
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R2-12 (Time: 14:37 - 14:39)
TitleDual Supply Voltage Assignment in 3D ICs Considering Thermal Effects
Author*Shu-Han Whi, Yu-Min Lee (National Chiao Tung Univ., Taiwan)
Pagepp. 178 - 183
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R2-13 (Time: 14:39 - 14:41)
TitleStudy of Multiple-Output Neuron MOS Current Mirror for Current-Steering Digital-to-Analog Converter
Author*Shuhei Yasumoto, Yuki Nobe, Akio Shimizu, Sumio Fukai (Saga Univ., Japan), Yohei Ishikawa (Ariake National College of Tech., Japan)
Pagepp. 184 - 189
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R2-14 (Time: 14:41 - 14:43)
TitleExtended Sequence Pair: A Finite Solution Space for Two-Directional Repeated Placement
Author*Mineo Kaneko, Takayuki Shibata (JAIST, Japan)
Pagepp. 190 - 195
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R2-15 (Time: 14:43 - 14:45)
TitleLSI Implementation Method of DES Cryptographic Circuit Utilizing Domino-RSL Gate Resistant to DPA Attack
Author*Kenji Kojima, Kazuki Okuyama, Katsuhiro Iwai, Mitsuru Shiozaki (Ritsumeikan Univ., Japan), Masaya Yoshikawa (Meijyo Univ., Japan), Takeshi Fujino (Ritsumeikan Univ., Japan)
Pagepp. 196 - 201
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R2-16 (Time: 14:45 - 14:47)
TitleThe Sizing of Sleep Transistors In Controlling Value Based Power Gating
Author*Lei Chen, Shinji Kimura (Waseda Univ., Japan)
Pagepp. 202 - 207
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R2-17 (Time: 14:47 - 14:49)
TitleA Verification Method of Pipeline Processing Behavior of Superconducting Single-Flux-Quantum Pulse Logic Circuits
Author*Kazuyoshi Takagi, Motoki Sato, Masamitsu Tanaka (Nagoya Univ., Japan), Naofumi Takagi (Kyoto Univ., Japan)
Pagepp. 208 - 213
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R2-18 (Time: 14:49 - 14:51)
TitleAn Incremental Synthesis Technique for ECO Based on Iterative Procedure for Error Diagnosis and Spare Cell Assignment
Author*Kosuke Watanabe, Hiroto Senzaki, Kosuke Shioki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 214 - 219
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R2-19 (Time: 14:51 - 14:53)
TitleError-Rate Prediction for Probabilistic Circuits with More General Structures
AuthorMark Lau, *Keck-Voon Ling, Arun Bhanu, Vincent Mooney (Nanyang Technological Univ., Singapore)
Pagepp. 220 - 225
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