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The 16th Workshop on Synthesis And System Integration of Mixed Information Technologies

Paper Session III: Logic and Physical Design (II)
Time: 10:15 - 12:00 Tuesday, October 19, 2010
Location: Ballroom
Chairs: Yasuhiro Takashima (Univ. of Kitakyushu, Japan), Jiun-Lang Huang (National Taiwan Univ., Taiwan)

R3-1 (Time: 10:15 - 10:17)
TitleIncreasing Yield Using Partially-Programmable Circuits
Author*Shigeru Yamashita (Ritsumeikan Univ., Japan), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo, Japan)
Pagepp. 237 - 242
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R3-2 (Time: 10:17 - 10:19)
TitleOn Handling Cell Placement with Exclusive Adjacent Symmetry Constraints for Analog IC Layout Design
Author*Shimpei Asano, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan)
Pagepp. 243 - 248
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R3-3 (Time: 10:19 - 10:21)
TitleA Low-Cost and Noise-Tolerant ADC BIST with On-the-Fly DNL/INL Calculation
AuthorKuo-Yu Chou, Ming-Huan Lu, Ping-Ying Kang, Xuan-Lun Huang, *Jiun-Lang Huang (National Taiwan Univ., Taiwan)
Pagepp. 249 - 253
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R3-4 (Time: 10:21 - 10:23)
TitleA Four-valude Adder Circuit Design with FG-MOS Transistors
Author*Yuya Wada, Koji Nishi, Akio Shimizu, Sumio Fukai (Saga Univ., Japan), Yohei Ishikawa (Ariake National College of Tech., Japan)
Pagepp. 254 - 259
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R3-5 (Time: 10:23 - 10:25)
TitleHigh-Level Synthesis of 3D IC Designs for TSV Number Minimization
AuthorChih-Hung Lee, *Shih-Hsu Huang, Chun-Hua Cheng (Chung Yuan Christian Univ., Taiwan)
Pagepp. 260 - 265
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R3-6 (Time: 10:25 - 10:27)
TitleAn IEEE 1500 Wrapper Sharing Technique on Reducing Test Cost
Author*Mao-Yin Wang, Ji-Jan Chen (ITRI, Taiwan)
Pagepp. 266 - 271
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R3-7 (Time: 10:27 - 10:29)
TitleAn Incremental Synthesis Technique Based on Error Diagnosis and Technology Remapping for Clusters
AuthorHiroto Senzaki, Kosuke Watanabe, Kosuke Shioki, Tetsuya Hirose, Nobutaka Kuroki, *Masahiro Numa (Kobe Univ., Japan)
Pagepp. 272 - 277
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R3-8 (Time: 10:29 - 10:31)
TitleA Single Layer Trunk Routing Using 45-Degree Lines within Critical Areas for PCB Routing
Author*Kyosuke Shinoda (Tokyo Inst. of Tech., Japan), Yukihide Kohira (Univ. of Aizu, Japan), Atsushi Takahashi (Osaka Univ., Japan)
Pagepp. 278 - 283
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R3-9 (Time: 10:31 - 10:33)
TitleClockless Handshaking Inter-chip Communication Applied in Daisy-chained Biomedical Signal Processing SoC
Author*Hong-Hui Chen, Tung-Chien Chen, Cheng-Yi Chiang, Liang-Gee Chen (National Taiwan Univ., Taiwan)
Pagepp. 284 - 289
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R3-10 (Time: 10:33 - 10:35)
TitleA New Statistical Maximum Operation for Gaussian Mixture Models Considering Cumulative Distribution Function Curve
Author*Shuji Tsukiyama (Chuo Univ., Japan), Masahiro Fukui (Ritsumeikan Univ., Japan)
Pagepp. 290 - 295
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R3-11 (Time: 10:35 - 10:37)
TitleMaximal Resilience for Reliability Enhancement in Interconnect Structure
AuthorChih-Yun Pai, *Shu-Min Li (National Sun Yat-sen Univ., Taiwan)
Pagepp. 296 - 301
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R3-12 (Time: 10:37 - 10:39)
TitleMinimizing Wirelength and Overflow of 3D-IC Global Routing by Signal-TSV Planning
Author*Guan-Hung Chen, Ke-Ren Dai, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Pagepp. 302 - 307
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R3-13 (Time: 10:39 - 10:41)
TitleBus-Driven Floorplanning With Bus Pin Assignment
Author*Po-Hsun Wu, Tsung-Yi Ho (National Cheng Kung Univ., Taiwan)
Pagepp. 308 - 313
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R3-14 (Time: 10:41 - 10:43)
TitleSystematic Yield Optimization for Restricted PPC Pattern Generation with Genetic Algorithm
Author*Katsuhiko Harazaki (Sharp Corp., Japan), Moritoshi Yasunaga (Univ. of Tsukuba, Japan)
Pagepp. 314 - 319
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R3-15 (Time: 10:43 - 10:45)
TitleClock Planning for Multi-Voltage and Multi-Mode Designs
Author*Chang-Cheng Tsai, Tzu-Hen Lin, Shin-Han Tsai, Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Pagepp. 320 - 324
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R3-16 (Time: 10:45 - 10:47)
TitleEfficient Random-Defect Aware Layer Assignment and Gridless Track Routing
Author*Yu-Wei Lee, Yen-Hung Lin, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Pagepp. 325 - 330
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R3-17 (Time: 10:47 - 10:49)
TitleAnalog Layout Generation based on Wiring Symmetry
Author*Yu-Ming Yang, Iris Hui-Ru Jiang (National Chiao Tung Univ., Taiwan)
Pagepp. 331 - 336
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R3-18 (Time: 10:49 - 10:51)
TitleAn Approach for Computation Efficiency Improvement of Power Grid Simulation by GPGPU
Author*Makoto Yokota, Yuuya Isoda, Tetsuya Hasegawa, Masahiro Fukui (Ritsumeikan Univ., Japan)
Pagepp. 337 - 342
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