The 16th Workshop on Synthesis And System Integration of Mixed Information Technologies
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Monday, October 18, 2010


Opening (Ballroom) 08:40 - 09:00
K1 (Ballroom) Keynote I 9:00 - 10:00
Coffee Break 10:00 - 10:15
R1 (Ballroom) Paper Session I: System Level Design and Design Experience (I) 10:15 - 12:00
Lunch Break 12:00 - 13:30
I1 (Ballroom) Invited Talk I 13:30 - 14:15
R2 (Ballroom) Paper Session II: Logic and Physical Design (I) 14:15 - 16:00
D (Ballroom) Panel Discussion 16:00 - 17:30
Banquet (Ballroom) 19:00 - 21:00

Tuesday, October 19, 2010


K2 (Ballroom) Keynote II 9:00 - 10:00
Coffee Break 10:00 - 10:15
R3 (Ballroom) Paper Session III: Logic and Physical Design (II) 10:15 - 12:00
Lunch Break 12:00 - 13:30
I2 (Ballroom) Invited Talk II 13:30 - 14:15
I3 (Ballroom) Invited Talk III 14:15 - 15:00
Coffee Break 15:00 - 15:15
R4 (Ballroom) Paper Session IV: System Level Design and Design Experience (II) 15:15 - 16:50
Closing 16:50 - 17:00

List of Papers

Remark: The presenter of each paper is marked with "*".

Monday, October 18, 2010

Keynote I
Time: 9:00 - 10:00 Monday, October 18, 2010
Location: Ballroom
Chair: Youn-Long Lin (National Tsing Hua Univ., Taiwan)

K1-1 (Time: 9:00 - 10:00)

Title	Energy Efficient Enterprise Computing Systems
Author	*Massoud Pedram (Univ. of Southern California, U.S.A.)
Page	p. 3
Detailed information (abstract, keywords, etc)

Paper Session I: System Level Design and Design Experience (I)
Time: 10:15 - 12:00 Monday, October 18, 2010
Location: Ballroom
Chairs: Rung-Bin Lin (Yuan Ze Univ., Taiwan), Youhua Shi (Waseda Univ., Japan)

R1-1 (Time: 10:15 - 10:17)

Title	Placing Static and Stack Data into a Scratch-Pad Memory for Reducing the Energy Consumption of Multi-task Applications
Author	*Lovic Gauthier, Tohru Ishihara (Kyushu Univ., Japan), Hideki Takase (Nagoya Univ., Japan), Hiroyuki Tomiyama (Ritsumeikan Univ., Japan), Hiroaki Takada (Nagoya Univ., Japan)
Page	pp. 7 - 12
Detailed information (abstract, keywords, etc)

R1-2 (Time: 10:17 - 10:19)

Title	Aggressive Register Unsharing with Selective FU Sharing in High-Level Synthesis
Author	*Yuko Hara-Azumi, Toshinobu Matsuba (Nagoya Univ., Japan), Hiroyuki Tomiyama (Ritsumeikan Univ., Japan), Shinya Honda, Hiroaki Takada (Nagoya Univ., Japan)
Page	pp. 13 - 18
Detailed information (abstract, keywords, etc)

R1-3 (Time: 10:19 - 10:21)

Title	Automatic Generation for Efficient Software TLM at Multiple Abstraction Layers
Author	Meng-Huan Wu, *Yi-Shan Lu, Wen-Chuan Lee, Chen-Yu Chuang, Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Page	pp. 19 - 24
Detailed information (abstract, keywords, etc)

R1-4 (Time: 10:21 - 10:23)

Title	Evaluation of Two Operating Systems for Lego Mindstorms NXT
Author	*Wing-Kwong Wong, Fu-Hsien Lin (National Yunlin Univ. of Science and Tech., Taiwan)
Page	pp. 25 - 30
Detailed information (abstract, keywords, etc)

R1-5 (Time: 10:23 - 10:25)

Title	Concord: A Configurable SoC Prototyping Platform
Author	Chih-Chyau Yang, *Chen-Yen Lin, Hui-Ming Lin, Yui-Chih Shih, Hsi-Tse Wu, Shi-Lun Chen, Tien-Ching Wang, Chien-Ming Wu, Chun-Ming Huang, Chin-Long Wey (National Chip Implementation Center, Taiwan)
Page	pp. 31 - 36
Detailed information (abstract, keywords, etc)

R1-6 (Time: 10:25 - 10:27)

Title	Generation Method of Decomposed Small Area Instruction Decoder for Configurable Processor
Author	*Hiroki Ohsawa, Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Page	pp. 37 - 41
Detailed information (abstract, keywords, etc)

R1-7 (Time: 10:27 - 10:29)

Title	A High-speed VLSI Architecture of Output Probability and Likelihood Score Computations for HMM-based Recognition Systems
Author	*Ryo Shimazaki, Kazuhiro Nakamura, Mashatoshi Yamamoto, Kazuyoshi Takagi (Nagoya Univ., Japan), Naofumi Takagi (Kyoto Univ., Japan)
Page	pp. 42 - 47
Detailed information (abstract, keywords, etc)

R1-8 (Time: 10:29 - 10:31)

Title	Improved Local Horizontal and Vertical Common Subexpression Elimination Method for Constant Multiple Multiplication
Author	*Yasuhiro Takahashi, Toshikazu Sekine (Gifu Univ., Japan), Michio Yokoyama (Yamagata Univ., Japan)
Page	pp. 48 - 53
Detailed information (abstract, keywords, etc)

R1-9 (Time: 10:31 - 10:33)

Title	Improved Normalized Image Reconstruction for Iris Recognition
Author	*Hyo Jin Nam, Harsh Durga Tiwari, Yong Beom Cho (Konkuk Univ., Republic of Korea)
Page	pp. 54 - 57
Detailed information (abstract, keywords, etc)

R1-10 (Time: 10:33 - 10:35)

Title	Inter-Island Delay Aware Communication Synthesis for Island-Based Distributed Register Architecture
Author	Juinn-Dar Huang, *Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou (National Chiao Tung Univ., Taiwan)
Page	pp. 58 - 63
Detailed information (abstract, keywords, etc)

R1-11 (Time: 10:35 - 10:37)

Title	MorFPGA: A Modularized FPGA-Based Embedded System Development Platform
Author	Yu-Tsang Chang, Chun-Ming Huang, Chien-Ming Wu, Chun-Yu Chen, *Yu-Sheng Lin, Chih-Ting Kuo, Ting-Chun Liu, Chin-Long Wey (National Chip Implementation Center, Taiwan)
Page	pp. 64 - 69
Detailed information (abstract, keywords, etc)

R1-12 (Time: 10:37 - 10:39)

Title	A Novel Design-Methodology for PCB Traces Ensuring High Signal-Integrity on Random Signals
Author	*Masami Ishiguro, Shohei Akita, Hiroki Shimada, Noriyuki Aibe (Univ. of Tsukuba, Japan), Ikuo Yoshihara (Univ. of Miyazaki, Japan), Moritoshi Yasunaga (Univ. of Tsukuba, Japan)
Page	pp. 70 - 75
Detailed information (abstract, keywords, etc)

R1-13 (Time: 10:39 - 10:41)

Title	A Novel IR-Drop Tolerant Scheduling for Reliability-Aware Datapaths
Author	*Keisuke Inoue, Mineo Kaneko (JAIST, Japan)
Page	pp. 76 - 81
Detailed information (abstract, keywords, etc)

R1-14 (Time: 10:41 - 10:43)

Title	A Physics-Based Compact Model for the 1/f Noise in p-type Si/SiGe/Si Heterostructure MOSFETs
Author	*Chia-Yu Chen (Stanford Univ., U.S.A.), Chi-Chao Wang, Yun Ye (Arizona State Univ., U.S.A.), Yang Liu (Stanford Univ., U.S.A.), Junko Sato-Iwanaga, Akira Inoue, Haruyuki Sorada (Panasonic Electronics, Japan), Yu Cao (Arizona State Univ., U.S.A.), Robert Dutton (Stanford Univ., U.S.A.)
Page	pp. 82 - 83
Detailed information (abstract, keywords, etc)

R1-15 (Time: 10:43 - 10:45)

Title	On Behavioral Modeling for Sigma-Delta Digital-to-Analog Converters with Accurate Timing Response
Author	*Hsin-Yu Luo, Hsiu-Wen Li, Xiao-Qian Chang, Chien-Nan Jimmy Liu (National Central Univ., Taiwan)
Page	pp. 84 - 89
Detailed information (abstract, keywords, etc)

R1-16 (Time: 10:45 - 10:47)

Title	Self-Tuning Metric and Control Policy to Optimally Trade-off Lifetime Performance-Power-Reliability
Author	*Evelyn Mintarno, Joelle Skaf (Stanford Univ., U.S.A.), Rui Zheng, Jyothi Velamala, Yu Cao (Arizona State Univ., U.S.A.), Stephen Boyd, Robert W. Dutton, Subhasish Mitra (Stanford Univ., U.S.A.)
Page	pp. 90 - 95
Detailed information (abstract, keywords, etc)

R1-17 (Time: 10:47 - 10:49)

Title	A Throughput-aware BusMesh NoC Configuration Algorithm Utilizing the Communication Rate between IP Cores
Author	*SeungJu Lee, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ., Japan)
Page	pp. 96 - 101
Detailed information (abstract, keywords, etc)

R1-18 (Time: 10:49 - 10:51)

Title	TSV-constrained Scan Chain Reordering for 3D ICs
Author	Wei-Ting Chen, Chia-Ching Chang, *Charles H.-P. Wen (National Chiao Tung Univ., Taiwan)
Page	pp. 102 - 107
Detailed information (abstract, keywords, etc)

Invited Talk I
Time: 13:30 - 14:15 Monday, October 18, 2010
Location: Ballroom
Chair: Hiroyuki Ochi (Kyoto Univ., Japan)

I1-1 (Time: 13:30 - 14:15)

Title	Smart Automobiles for Future Ecosystems
Author	*Hideaki Ishihara (Denso, Japan)
Page	p. 111
Detailed information (abstract, keywords, etc)

Paper Session II: Logic and Physical Design (I)
Time: 14:15 - 16:00 Monday, October 18, 2010
Location: Ballroom
Chairs: Takashi Horiyama (Saitama Univ., Japan), Hui-Ru Iris Jiang (National Chiao Tung Univ., Taiwan)

R2-1 (Time: 14:15 - 14:17)

Title	Stable-LSE based Analytical Placement with Overlap Removable Length
Author	*Masatomo Kuwano, Yasuhiro Takashima (Univ. of Kitakyushu, Japan)
Page	pp. 115 - 120
Detailed information (abstract, keywords, etc)

R2-2 (Time: 14:17 - 14:19)

Title	Metal Balance Based Clock Construction to Minimize Process Variation Effect
Author	*Zhi-Wei Chen (Inst. of Information Industry, Taiwan), Hung-Ming Chen, Ren-Jie Lee, Chun-Kai Wang (National Chiao Tung Univ., Taiwan)
Page	pp. 121 - 125
Detailed information (abstract, keywords, etc)

R2-3 (Time: 14:19 - 14:21)

Title	Circuit Performance Degradation on FPGAs Considering NBTI and Process Variations
Author	*Michitarou Yabuuchi, Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan)
Page	pp. 126 - 129
Detailed information (abstract, keywords, etc)

R2-4 (Time: 14:21 - 14:23)

Title	Rover: Routing on Via-Configurable Fabrics for Standard-Cell-Like Structured ASICs
Author	*Liang-Chi Lai, Hsih-Han Chang, Rung-Bin Lin (Yuan Ze Univ., Taiwan)
Page	pp. 130 - 135
Detailed information (abstract, keywords, etc)

R2-5 (Time: 14:23 - 14:25)

Title	A Physical-Location-Aware Fault Redistribution for Maximum IR-Drop Reduction
Author	*Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang (National Tsing Hua Univ., Taiwan)
Page	pp. 136 - 141
Detailed information (abstract, keywords, etc)

R2-6 (Time: 14:25 - 14:27)

Title	Redundant Via Insertion under Timing Constraints
Author	*Chi-Wen Pan, Yu-Min Lee (National Chiao Tung Univ., Taiwan)
Page	pp. 142 - 147
Detailed information (abstract, keywords, etc)

R2-7 (Time: 14:27 - 14:29)

Title	Optimal Wiring Topology for Electromigration Avoidance
Author	Iris Hui-Ru Jiang (National Chiao Tung Univ., Taiwan), Hua-Yu Chang (National Taiwan Univ., Taiwan), *Chih-Long Chang (National Chiao Tung Univ., Taiwan)
Page	pp. 148 - 153
Detailed information (abstract, keywords, etc)

R2-8 (Time: 14:29 - 14:31)

Title	Iterative 3D Partitioning for Through-Silicon Via Minimization
Author	*Ya-Shih Huang, Yang-Hsiang Liu, Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Page	pp. 154 - 159
Detailed information (abstract, keywords, etc)

R2-9 (Time: 14:31 - 14:33)

Title	A Novel Zone-Based ILP Track Routing
Author	*Ke-Ren Dai, Yi-Chun Lin, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Page	pp. 160 - 165
Detailed information (abstract, keywords, etc)

R2-10 (Time: 14:33 - 14:35)

Title	3D-AADI: An Adaptive and Integrable Thermal Simulator According to ADI Concept for 3D IC Physical Design Flow
Author	*Sophie Ting-Jung Li, Yu-Min Lee (National Chiao Tung Univ., Taiwan)
Page	pp. 166 - 171
Detailed information (abstract, keywords, etc)

R2-11 (Time: 14:35 - 14:37)

Title	An ILP-based Diagnosis Framework For Multiple Open-Segment Defects
Author	Chen-Yuan Kao, Chien-Hui Liao, *Charles Hung-Ping Wen (National Chiao Tung Univ., Taiwan)
Page	pp. 172 - 177
Detailed information (abstract, keywords, etc)

R2-12 (Time: 14:37 - 14:39)

Title	Dual Supply Voltage Assignment in 3D ICs Considering Thermal Effects
Author	*Shu-Han Whi, Yu-Min Lee (National Chiao Tung Univ., Taiwan)
Page	pp. 178 - 183
Detailed information (abstract, keywords, etc)

R2-13 (Time: 14:39 - 14:41)

Title	Study of Multiple-Output Neuron MOS Current Mirror for Current-Steering Digital-to-Analog Converter
Author	*Shuhei Yasumoto, Yuki Nobe, Akio Shimizu, Sumio Fukai (Saga Univ., Japan), Yohei Ishikawa (Ariake National College of Tech., Japan)
Page	pp. 184 - 189
Detailed information (abstract, keywords, etc)

R2-14 (Time: 14:41 - 14:43)

Title	Extended Sequence Pair: A Finite Solution Space for Two-Directional Repeated Placement
Author	*Mineo Kaneko, Takayuki Shibata (JAIST, Japan)
Page	pp. 190 - 195
Detailed information (abstract, keywords, etc)

R2-15 (Time: 14:43 - 14:45)

Title	LSI Implementation Method of DES Cryptographic Circuit Utilizing Domino-RSL Gate Resistant to DPA Attack
Author	*Kenji Kojima, Kazuki Okuyama, Katsuhiro Iwai, Mitsuru Shiozaki (Ritsumeikan Univ., Japan), Masaya Yoshikawa (Meijyo Univ., Japan), Takeshi Fujino (Ritsumeikan Univ., Japan)
Page	pp. 196 - 201
Detailed information (abstract, keywords, etc)

R2-16 (Time: 14:45 - 14:47)

Title	The Sizing of Sleep Transistors In Controlling Value Based Power Gating
Author	*Lei Chen, Shinji Kimura (Waseda Univ., Japan)
Page	pp. 202 - 207
Detailed information (abstract, keywords, etc)

R2-17 (Time: 14:47 - 14:49)

Title	A Verification Method of Pipeline Processing Behavior of Superconducting Single-Flux-Quantum Pulse Logic Circuits
Author	*Kazuyoshi Takagi, Motoki Sato, Masamitsu Tanaka (Nagoya Univ., Japan), Naofumi Takagi (Kyoto Univ., Japan)
Page	pp. 208 - 213
Detailed information (abstract, keywords, etc)

R2-18 (Time: 14:49 - 14:51)

Title	An Incremental Synthesis Technique for ECO Based on Iterative Procedure for Error Diagnosis and Spare Cell Assignment
Author	*Kosuke Watanabe, Hiroto Senzaki, Kosuke Shioki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 214 - 219
Detailed information (abstract, keywords, etc)

R2-19 (Time: 14:51 - 14:53)

Title	Error-Rate Prediction for Probabilistic Circuits with More General Structures
Author	Mark Lau, *Keck-Voon Ling, Arun Bhanu, Vincent Mooney (Nanyang Technological Univ., Singapore)
Page	pp. 220 - 225
Detailed information (abstract, keywords, etc)

Panel Discussion
Time: 16:00 - 17:30 Monday, October 18, 2010
Location: Ballroom
Moderator: Tsun-Chieh Chiang (ITRI)

D-1 (Time: 16:00 - 17:30)

Title	Is Automotive Electronics Creating New Opportunities for Semiconductor?
Author	Organizers: Cheng-Wen Wu (ITRI, Taiwan), Jing-Jou Tang (Southern Taiwan Univ., Taiwan), Moderator: Tsun-Chieh Chiang (ITRI, Taiwan), Panelists: Ching-Yao Chan (Univ. of California, Berkeley, U.S.A.), Hsueh-Lung Liao (ARTC, Taiwan), Kenneth Ma, James Wang (ITRI, Taiwan)
Page	pp. 229 - 230
Detailed information (abstract, keywords, etc)

Tuesday, October 19, 2010

Keynote II
Time: 9:00 - 10:00 Tuesday, October 19, 2010
Location: Ballroom
Chair: Youn-Long Lin (National Tsing Hua Univ., Taiwan)

K2-1 (Time: 9:00 - 10:00)

Title	Workflow Approach to Building User-Centric Automation and Assistive Devices and Systems
Author	*Jane W. S. Liu (Academia Sinica, Taiwan)
Page	pp. 233 - 234
Detailed information (abstract, keywords, etc)

Paper Session III: Logic and Physical Design (II)
Time: 10:15 - 12:00 Tuesday, October 19, 2010
Location: Ballroom
Chairs: Yasuhiro Takashima (Univ. of Kitakyushu, Japan), Jiun-Lang Huang (National Taiwan Univ., Taiwan)

R3-1 (Time: 10:15 - 10:17)

Title	Increasing Yield Using Partially-Programmable Circuits
Author	*Shigeru Yamashita (Ritsumeikan Univ., Japan), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo, Japan)
Page	pp. 237 - 242
Detailed information (abstract, keywords, etc)

R3-2 (Time: 10:17 - 10:19)

Title	On Handling Cell Placement with Exclusive Adjacent Symmetry Constraints for Analog IC Layout Design
Author	*Shimpei Asano, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan)
Page	pp. 243 - 248
Detailed information (abstract, keywords, etc)

R3-3 (Time: 10:19 - 10:21)

Title	A Low-Cost and Noise-Tolerant ADC BIST with On-the-Fly DNL/INL Calculation
Author	Kuo-Yu Chou, Ming-Huan Lu, Ping-Ying Kang, Xuan-Lun Huang, *Jiun-Lang Huang (National Taiwan Univ., Taiwan)
Page	pp. 249 - 253
Detailed information (abstract, keywords, etc)

R3-4 (Time: 10:21 - 10:23)

Title	A Four-valude Adder Circuit Design with FG-MOS Transistors
Author	*Yuya Wada, Koji Nishi, Akio Shimizu, Sumio Fukai (Saga Univ., Japan), Yohei Ishikawa (Ariake National College of Tech., Japan)
Page	pp. 254 - 259
Detailed information (abstract, keywords, etc)

R3-5 (Time: 10:23 - 10:25)

Title	High-Level Synthesis of 3D IC Designs for TSV Number Minimization
Author	Chih-Hung Lee, *Shih-Hsu Huang, Chun-Hua Cheng (Chung Yuan Christian Univ., Taiwan)
Page	pp. 260 - 265
Detailed information (abstract, keywords, etc)

R3-6 (Time: 10:25 - 10:27)

Title	An IEEE 1500 Wrapper Sharing Technique on Reducing Test Cost
Author	*Mao-Yin Wang, Ji-Jan Chen (ITRI, Taiwan)
Page	pp. 266 - 271
Detailed information (abstract, keywords, etc)

R3-7 (Time: 10:27 - 10:29)

Title	An Incremental Synthesis Technique Based on Error Diagnosis and Technology Remapping for Clusters
Author	Hiroto Senzaki, Kosuke Watanabe, Kosuke Shioki, Tetsuya Hirose, Nobutaka Kuroki, *Masahiro Numa (Kobe Univ., Japan)
Page	pp. 272 - 277
Detailed information (abstract, keywords, etc)

R3-8 (Time: 10:29 - 10:31)

Title	A Single Layer Trunk Routing Using 45-Degree Lines within Critical Areas for PCB Routing
Author	*Kyosuke Shinoda (Tokyo Inst. of Tech., Japan), Yukihide Kohira (Univ. of Aizu, Japan), Atsushi Takahashi (Osaka Univ., Japan)
Page	pp. 278 - 283
Detailed information (abstract, keywords, etc)

R3-9 (Time: 10:31 - 10:33)

Title	Clockless Handshaking Inter-chip Communication Applied in Daisy-chained Biomedical Signal Processing SoC
Author	*Hong-Hui Chen, Tung-Chien Chen, Cheng-Yi Chiang, Liang-Gee Chen (National Taiwan Univ., Taiwan)
Page	pp. 284 - 289
Detailed information (abstract, keywords, etc)

R3-10 (Time: 10:33 - 10:35)

Title	A New Statistical Maximum Operation for Gaussian Mixture Models Considering Cumulative Distribution Function Curve
Author	*Shuji Tsukiyama (Chuo Univ., Japan), Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 290 - 295
Detailed information (abstract, keywords, etc)

R3-11 (Time: 10:35 - 10:37)

Title	Maximal Resilience for Reliability Enhancement in Interconnect Structure
Author	Chih-Yun Pai, *Shu-Min Li (National Sun Yat-sen Univ., Taiwan)
Page	pp. 296 - 301
Detailed information (abstract, keywords, etc)

R3-12 (Time: 10:37 - 10:39)

Title	Minimizing Wirelength and Overflow of 3D-IC Global Routing by Signal-TSV Planning
Author	*Guan-Hung Chen, Ke-Ren Dai, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Page	pp. 302 - 307
Detailed information (abstract, keywords, etc)

R3-13 (Time: 10:39 - 10:41)

Title	Bus-Driven Floorplanning With Bus Pin Assignment
Author	*Po-Hsun Wu, Tsung-Yi Ho (National Cheng Kung Univ., Taiwan)
Page	pp. 308 - 313
Detailed information (abstract, keywords, etc)

R3-14 (Time: 10:41 - 10:43)

Title	Systematic Yield Optimization for Restricted PPC Pattern Generation with Genetic Algorithm
Author	*Katsuhiko Harazaki (Sharp Corp., Japan), Moritoshi Yasunaga (Univ. of Tsukuba, Japan)
Page	pp. 314 - 319
Detailed information (abstract, keywords, etc)

R3-15 (Time: 10:43 - 10:45)

Title	Clock Planning for Multi-Voltage and Multi-Mode Designs
Author	*Chang-Cheng Tsai, Tzu-Hen Lin, Shin-Han Tsai, Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Page	pp. 320 - 324
Detailed information (abstract, keywords, etc)

R3-16 (Time: 10:45 - 10:47)

Title	Efficient Random-Defect Aware Layer Assignment and Gridless Track Routing
Author	*Yu-Wei Lee, Yen-Hung Lin, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Page	pp. 325 - 330
Detailed information (abstract, keywords, etc)

R3-17 (Time: 10:47 - 10:49)

Title	Analog Layout Generation based on Wiring Symmetry
Author	*Yu-Ming Yang, Iris Hui-Ru Jiang (National Chiao Tung Univ., Taiwan)
Page	pp. 331 - 336
Detailed information (abstract, keywords, etc)

R3-18 (Time: 10:49 - 10:51)

Title	An Approach for Computation Efficiency Improvement of Power Grid Simulation by GPGPU
Author	*Makoto Yokota, Yuuya Isoda, Tetsuya Hasegawa, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 337 - 342
Detailed information (abstract, keywords, etc)

Invited Talk II
Time: 13:30 - 14:15 Tuesday, October 19, 2010
Location: Ballroom
Chair: Ting-Chi Wang (National Tsing Hua Univ., Taiwan)

I2-1 (Time: 13:30 - 14:15)

Title	Recent Research Development in Mixed-Size Circuit Placement
Author	Meng-Kai Hsu, *Yao-Wen Chang (National Taiwan Univ., Taiwan)
Page	pp. 345 - 351
Detailed information (abstract, keywords, etc)

Invited Talk III
Time: 14:15 - 15:00 Tuesday, October 19, 2010
Location: Ballroom
Chair: Ting-Chi Wang (National Tsing Hua Univ., Taiwan)

I3-1 (Time: 14:15 - 15:00)

Title	3D Die-Stacking: Challenges and Opportunities for Computer Architecture
Author	*Gabriel H. Loh (Advanced Micro Devices, U.S.A.)
Page	p. 355
Detailed information (abstract, keywords, etc)

Paper Session IV: System Level Design and Design Experience (II)
Time: 15:15 - 16:50 Tuesday, October 19, 2010
Location: Ballroom
Chairs: Masanori Muroyama (Tohoku Univ., Japan), Lih-Yih Chiou (National Cheng Kung Univ., Taiwan)

R4-1 (Time: 15:15 - 15:17)

Title	A Regular Expression Matching Circuit Based on a Modular Non-Deterministic Finite Automaton with Multi-Character Transition
Author	*Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech., Japan)
Page	pp. 359 - 364
Detailed information (abstract, keywords, etc)

R4-2 (Time: 15:17 - 15:19)

Title	Acceleration of a SAT Based Solver for Minimum Cost Satisfiability Problems Using Optimized Boolean Constraint Propagation
Author	*Xin Zhang (Waseda Univ., Japan), Peilin Liu (Shanghai Jiao Tong Univ., China), Shinji Kimura (Waseda Univ., Japan)
Page	pp. 365 - 370
Detailed information (abstract, keywords, etc)

R4-3 (Time: 15:19 - 15:21)

Title	Circuit Synthesis for Fast Memory Access in System LSI
Author	*Kazuya Kishida, Takashi Kambe (Kinki Univ., Japan)
Page	pp. 371 - 376
Detailed information (abstract, keywords, etc)

R4-4 (Time: 15:21 - 15:23)

Title	Clock Gating Optimization with Delay-Matching Cells
Author	*Shih-Jung Hsu, Rung-Bin Lin (Yuan Ze Univ., Taiwan)
Page	pp. 377 - 382
Detailed information (abstract, keywords, etc)

R4-5 (Time: 15:23 - 15:25)

Title	Design and Evaluation of Digital Receiver for Low Power Wireless Communication
Author	*Kazuki Ohya, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Page	pp. 383 - 388
Detailed information (abstract, keywords, etc)

R4-6 (Time: 15:25 - 15:27)

Title	Design and Verification of an Ultra-Low-Power Active RFID Tag with Multiple Power Domains
Author	*Kenichi Agawa, Massimo Alioto, Wenting Zhou, Tsung-Te Liu, Louis Alarcon, Kimiya Hajkazemshirazi, Mervin John, Jesse Richmond, Wen Li, Jan Rabaey (Univ. of California, Berkeley, U.S.A.)
Page	pp. 389 - 394
Detailed information (abstract, keywords, etc)

R4-7 (Time: 15:27 - 15:29)

Title	Device Simulation and Experimental Measurement of High-Voltage Unified-CBiCMOS Buffer Driver for Ultra-High-Speed CCD Image Sensors
Author	Toshiaki Koike-Akino (Harvard Univ., U.S.A.), Takashi Hamahata, *Toshiro Akino, Takeharu Goji Etoh (Kinki Univ., Japan)
Page	pp. 395 - 400
Detailed information (abstract, keywords, etc)

R4-8 (Time: 15:29 - 15:31)

Title	Efficient Multiple Regular Expression Matching on FPGAs based on Extended SHIFT-AND Method
Author	*Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, Yoshikazu Miyanaga (Hokkaido Univ., Japan)
Page	pp. 401 - 406
Detailed information (abstract, keywords, etc)

R4-9 (Time: 15:31 - 15:33)

Title	Energy-Aware Partitioning Using a Multi-Objective Genetic Algorithm
Author	Lih-Yih Chiou, Yi-Siou Chen, *Ya-Lun Jian (National Cheng Kung Univ., Taiwan)
Page	pp. 407 - 411
Detailed information (abstract, keywords, etc)

R4-10 (Time: 15:33 - 15:35)

Title	An Extension of Systolic Regular Expression Matching Hardware for Handling Iteration of Strings Using Quantifiers
Author	*Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ., Japan)
Page	pp. 412 - 417
Detailed information (abstract, keywords, etc)

R4-11 (Time: 15:35 - 15:37)

Title	A Novel Timing Synchronization Method for Fast and Accurate Multi-Core Instruction-Set Simulators
Author	Meng-Huan Wu, *Fan-Wei Yu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Page	pp. 418 - 423
Detailed information (abstract, keywords, etc)

R4-12 (Time: 15:37 - 15:39)

Title	A Power Efficient Unified Gated Flip-Flop
Author	*Takumi Okuhira, Tohru Ishihara (Kyushu Univ., Japan)
Page	pp. 424 - 429
Detailed information (abstract, keywords, etc)

R4-13 (Time: 15:39 - 15:41)

Title	Quantitative Graph-Based Minimal Queue Sizing for Throughput Optimization in Latency-Insensitive Designs
Author	Juinn-Dar Huang, *Yi-Hang Chen, Ya-Chien Ho (National Chiao Tung Univ., Taiwan)
Page	pp. 430 - 435
Detailed information (abstract, keywords, etc)

R4-14 (Time: 15:41 - 15:43)

Title	A Reconfigurable Layout Method and Evaluation for Network On Chip
Author	*Yuichi Nakamura (NEC Corp., Japan), Marcello Lajolo (NEC, U.S.A.)
Page	pp. 436 - 441
Detailed information (abstract, keywords, etc)

R4-15 (Time: 15:43 - 15:45)

Title	RER: a Tuning Tool for Implementing a Computational Pipeline Across Multiple FPGAs
Author	Hirokazu Morishita, *Kenta Inakagata (Keio Univ., Japan), Yasunori Osana (Seikei Univ., Japan), Naoyuki Fujita (JAXA, Japan), Hideharu Amano (Keio Univ., Japan)
Page	pp. 442 - 447
Detailed information (abstract, keywords, etc)

R4-16 (Time: 15:45 - 15:47)

Title	Soft-error Tolerability Analysis for Triplicated Circuit on an FPGA
Author	*Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ., Japan)
Page	pp. 448 - 453
Detailed information (abstract, keywords, etc)

R4-17 (Time: 15:47 - 15:49)

Title	A Tile Based Reconfigurable Architecture with Dual ALU-array/Processor Operating Mode Capability
Author	Shin'ichi Kouyama, Masayuki Hiromoto (Kyoto Univ., Japan), Yukihiro Nakamura (Ritsumeikan Univ., Japan), *Hiroyuki Ochi (Kyoto Univ., Japan)
Page	pp. 454 - 459
Detailed information (abstract, keywords, etc)

R4-18 (Time: 15:49 - 15:51)

Title	VLSI Architecture of V-AMDF based Pitch Detection for Tonal Speech Recognizer
Author	*Jirabhorn Chaiwongsai, Werapon Chiracharit, Kosin Chamnongthai (King Mongkut’s Univ. of Tech. Thonburi, Thailand), Yoshikazu Miyanaga (Hokkaido Univ., Japan), Kohji Higuchi (Univ. of Electro-Communications, Japan)
Page	pp. 460 - 465
Detailed information (abstract, keywords, etc)

The 16th Workshop on Synthesis And System Integration of Mixed Information Technologies Technical Program

Session Schedule

List of Papers

The 16th Workshop on Synthesis And System Integration of Mixed Information Technologies
Technical Program