Title | High Speed Approximation Feature Extraction in CAD System for Colorectal Endoscopic Images with NBI Magnification |
Author | *Tsubasa Mishima, Satoshi Shigemi, Anh-Tuan Hoang, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Rie Miyaki, Taiji Matsuo, Shigeto Yoshida, Shinji Tanaka (Hiroshima Univ., Japan) |
Page | pp. 208 - 213 |
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Title | A Fixed-Length Routing Method Based on the Color-Coding Algorithm |
Author | *Tieyuan Pan, Yasuhiro Takashima (Univ. of Kitakyushu, Japan) |
Page | pp. 214 - 219 |
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Title | Retiming of Single Flux Quantum Logic Circuits for Flip-Flop Reduction |
Author | *Nobutaka Kito (Chukyo Univ., Japan), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ., Japan) |
Page | pp. 220 - 225 |
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Title | Forwarding Unit Generation with Runtime Dependency Analysis in High-Level Synthesis |
Author | *Shingo Kusakabe, Kenshu Seto (Tokyo City Univ., Japan) |
Page | pp. 226 - 230 |
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Title | An NFA-Based Programmable Regular Expression Matching Engine Highly Suitable for FPGA Implementation |
Author | *Hiroki Takaguchi, Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ., Japan) |
Page | pp. 231 - 236 |
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Title | Graphillion: ZDD-Based Software Library for Very Large Sets of Graphs |
Author | Takeru Inoue, *Hiroaki Iwashita (JST, Japan), Jun Kawahara (NAIST, Japan), Shin-ichi Minato (Hokkaido Univ., Japan) |
Page | pp. 237 - 242 |
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Title | Clock Jitter Compensation for Continuous-Time Sigma-Delta Modulator Through Divided-by-N Feedback DAC |
Author | *Zong-Yi Chen, Chung-Chih Hung (National Chiao Tung Univ., Taiwan) |
Page | pp. 243 - 247 |
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Title | Simultaneous Escape Routing Considering Length Matching of Differential Pairs |
Author | Yen-Jung Lee, *Hung-Ming Chen, Ching-Yu Chin (National Chiao Tung Univ., Taiwan) |
Page | pp. 248 - 252 |
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Title | Technology Remapping Based on Multiple Solutions for Post-Mask Functional ECO |
Author | *Yudai Kabata, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
Page | pp. 253 - 258 |
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Title | A Fast Trace-Driven Heterogeneous L1 Cache Configuration Simulator for Dual-Core Processors |
Author | *Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ., Japan) |
Page | pp. 259 - 260 |
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Title | A Dynamic Offload Scheduler for Spatial Multitasking on Intel Xeon Phi Coprocessor |
Author | *Takamichi Miyamoto, Kazuhisa Ishizaka, Takeo Hosomi (NEC, Japan) |
Page | pp. 261 - 266 |
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Title | A Restricted Dynamically Reconfigurable Architecture for Low Power Processors |
Author | *Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ., Japan) |
Page | pp. 267 - 268 |
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Title | A Processor Architecture for Motion Sensing Systems Using Accelerometer |
Author | *Takashi Matsuo, Arif Ullah Khan (Osaka Univ., Japan), Takashi Hamabe (MICRONIX, Japan), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan) |
Page | pp. 269 - 274 |
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Title | Radiation-Hard Layout Structures on Bulk and SOI Process by Device-Level Simulations |
Author | *Kuiyuan Zhang, Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan) |
Page | pp. 275 - 279 |
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Title | Event Modeling Method for Verification of Power Analysis Attacks |
Author | *Kyota Sugioka, Toshiya Asai, Masaya Yoshikawa (Meijo Univ., Japan) |
Page | pp. 280 - 281 |
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Title | A Variable-Length String Matching Circuit Based On SeqBDDs |
Author | *Atsushi Matsuo, Yasunori Takagi (Ritsumeikan Univ., Japan), Hiroki Nakahara (Kagoshima Univ., Japan), Shigeru Yamashita (Ritsumeikan Univ., Japan) |
Page | pp. 282 - 287 |
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Title | An Image Compression Method for Frame Memory Size Reduction Using Local Feature of Images |
Author | *Yuki Fukuhara (Osaka Univ., Japan), Akihisa Yamada (Sharp/Osaka Univ., Japan), Takao Onoye (Osaka Univ., Japan) |
Page | pp. 288 - 289 |
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