SASIMI 2013
The 18th Workshop on Synthesis And System Integration of Mixed Information Technologies
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Monday, October 21, 2013


Opening (Tanchō-Hakuchō 1) 9:00 - 10:00
K1 (Tanchō-Hakuchō 1) Keynote Speech I 10:00 - 11:00
R1 (Tanchō-Hakuchō 1 & Kujyaku) Poster I 11:00 - 12:10
Lunch Break 12:10 - 13:40
I1 (Tanchō-Hakuchō 1) Invited Talk I 13:40 - 14:40
R2 (Tanchō-Hakuchō 1 & Kujyaku) Poster II 14:40 - 15:50
K2 (Tanchō-Hakuchō 1) Keynote Speech II 15:50 - 16:50
R3 (Tanchō-Hakuchō 1 & Kujyaku) Poster III 16:50 - 18:00
Banquet (Hakuchō) 18:30 - 20:30

Tuesday, October 22, 2013


I2 (Tanchō-Hakuchō 1) Invited Talk II 9:00 - 10:00
R4 (Tanchō-Hakuchō 1 & Kujyaku) Poster IV 10:00 - 11:30
Lunch Break 11:30 - 13:00
I3 (Tanchō-Hakuchō 1) Invited Talk III 13:00 - 14:00
D (Tanchō-Hakuchō 1) Panel Discussion 14:00 - 15:30
R5 (Tanchō-Hakuchō 1 & Kujyaku) Poster V 15:30 - 17:00
Closing (Tanchō-Hakuchō 1) 17:00 - 17:10

List of Papers

Remark: The presenter of each paper is marked with "*".

Monday, October 21, 2013

Keynote Speech I
Time: 10:00 - 11:00 Monday, October 21, 2013
Location: Tanchō-Hakuchō 1
Chair: Nagisa Ishiura (Kwansei Gakuin Univ., Japan)

K1 (Time: 10:00 - 11:00)

Title	Scaling the Many-Memory Wall for Many-Core Architectures
Author	*Nikil Dutt (Univ. of California, Irvine, U.S.A.)
Page	p. 1
Detailed information (abstract, keywords, etc)
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Poster I
Time: 11:00 - 12:10 Monday, October 21, 2013
Location: Tanchō-Hakuchō 1 & Kujyaku
Chairs: Kouichirou Yamashita (Fujitsu Labs., Japan), SeungJu Lee (Waseda Univ., Japan)

R1-1 (Time: 11:00 - 11:02)

Title	A Novel Fast and Accurate Hot Spot Detection Method with Prüfer Code Layout Encoding
Author	*Hong-Yan Su, Chieh-Chu Chen, Yih-Lang Li (National Chiao Tung Univ., Taiwan), An-Chun Tu, Chuh-Jen Wu, Chen-Ming Huang (TSMC, Taiwan)
Page	pp. 2 - 7
Detailed information (abstract, keywords, etc)

R1-2 (Time: 11:02 - 11:04)

Title	Implementation of Protocol Independent Control-Intensive Design in High-Level Synthesis
Author	Tung-Hua Yeh, Jen-Chieh Yeh (ITRI, Taiwan), *Qiang Zhu (Cadence Design Systems, Japan)
Page	pp. 8 - 12
Detailed information (abstract, keywords, etc)

R1-3 (Time: 11:04 - 11:06)

Title	Evaluation of On-Chip Decoupling Capacitor's Effect on AES Cryptographic Circuit
Author	*Tsunato Nakai, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino (Ritsumeikan Univ., Japan)
Page	pp. 13 - 18
Detailed information (abstract, keywords, etc)
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R1-4 (Time: 11:06 - 11:08)

Title	A Real-Time Peak Load Shaving with Error Compensation of Residential Load/PV Power Generation Forecasting
Author	*Hide Nishihara, Ittetsu Taniguchi, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 19 - 24
Detailed information (abstract, keywords, etc)

R1-5 (Time: 11:08 - 11:10)

Title	A Design of CMOS On-Chip Photovoltaic Device and Regulated DC-DC Converter for Micro System
Author	*Haruki Ono, Kazuki Nomura, Nobuhiko Nakano (Keio Univ., Japan)
Page	pp. 25 - 27
Detailed information (abstract, keywords, etc)
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R1-6 (Time: 11:10 - 11:12)

Title	An Error Diagnosis Technique Using QBF Solver to Fix LUT Functions
Author	*Naoki Katayama, Hiroyuki Sakamoto, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 28 - 33
Detailed information (abstract, keywords, etc)

R1-7 (Time: 11:12 - 11:14)

Title	Energy-Efficient Dynamic Voltage and Frequency Scaling by P/N-Performance Self-Adjustment Using Adaptive Body Bias
Author	*A.K.M. Mahfuzul Islam, Norihiro Kamae, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 34 - 39
Detailed information (abstract, keywords, etc)

R1-8 (Time: 11:14 - 11:16)

Title	A Nested Loop Pipelining in C Descriptions for System LSI Design
Author	*Masahiro Nambu, Takashi Kambe (Kinki Univ., Japan), Shuji Tsukiyama (Chuo Univ., Japan)
Page	pp. 40 - 43
Detailed information (abstract, keywords, etc)
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R1-9 (Time: 11:16 - 11:18)

Title	General Position-Based Weighted Round-Robin Arbitration for Arbitrary Traffic Patterns
Author	*Hanmin Park, Kiyoung Choi (Seoul National Univ., Republic of Korea)
Page	pp. 44 - 49
Detailed information (abstract, keywords, etc)

R1-10 (Time: 11:18 - 11:20)

Title	Memory Management for Dual-Addressing Memory Architecture
Author	*Ting-Wei Hong, Yen-Hao Chen, Yi-Yu Liu (Yuan Ze Univ., Taiwan)
Page	pp. 50 - 55
Detailed information (abstract, keywords, etc)
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R1-11 (Time: 11:20 - 11:22)

Title	Alpha-Gamma Data Compression Method for Artificial Vision Systems Using Visual Cortex Stimulation
Author	*Tomoki Sugiura, Arif Ullah Khan, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Page	pp. 56 - 61
Detailed information (abstract, keywords, etc)
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R1-12 (Time: 11:22 - 11:24)

Title	An Efficient Test Pattern Generator -Mersenne Twister-
Author	Hiroshi Iwata, *Sayaka Satonaka, Ken'ichi Yamaguchi (Nara National College of Tech., Japan)
Page	pp. 62 - 67
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R1-13 (Time: 11:24 - 11:26)

Title	Power Optimization of a Micro-Controller with Silicon on Thin Buried Oxide
Author	*Kuniaki Kitamori, Hongliang Su, Hideharu Amano (Keio Univ., Japan)
Page	pp. 68 - 73
Detailed information (abstract, keywords, etc)
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Invited Talk I
Time: 13:40 - 14:40 Monday, October 21, 2013
Location: Tanchō-Hakuchō 1
Chair: Nagisa Ishiura (Kwansei Gakuin Univ., Japan)

I1 (Time: 13:40 - 14:40)

Title	Computer-Aided Design of Electric Vehicle Hybrid Energy Storage System
Author	Sangyoung Park, Younghyun Kim, *Naehyuck Chang (Seoul National Univ., Republic of Korea)
Page	pp. 74 - 75
Detailed information (abstract, keywords, etc)

Poster II
Time: 14:40 - 15:50 Monday, October 21, 2013
Location: Tanchō-Hakuchō 1 & Kujyaku
Chairs: Kenshu Seto (Tokyo City Univ., Japan), Hiroshi Saito (Univ. of Aizu, Japan)

R2-1 (Time: 14:40 - 14:42)

Title	Place-and-Route Algorithms for a Reliability-Oriented Coarse-Grained Reconfigurable Architecture Using Time Redundancy
Author	*Takashi Imagawa, Masayuki Hiromoto (Kyoto Univ., Japan), Hiroshi Tsutsui (Hokkaido Univ., Japan), Hiroyuki Ochi (Ritsumeikan Univ., Japan), Takashi Sato (Kyoto Univ., Japan)
Page	pp. 76 - 81
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R2-2 (Time: 14:42 - 14:44)

Title	Power Analysis Resistant IP Core Using IO-Masked Dual-Rail ROM for Easy Implementation into Low-Power Area-Efficient Cryptographic LSIs
Author	*Megumi Shibatani, Mitsuru Shiozaki, Yuki Hashimoto, Takaya Kubota, Takeshi Fujino (Ritsumeikan Univ., Japan)
Page	pp. 82 - 87
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R2-3 (Time: 14:44 - 14:46)

Title	Scaling up Size and Number of Expressions in Random Testing of Arithmetic Optimization of C Compilers
Author	Eriko Nagai (Fujitsu Systems West, Japan), *Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
Page	pp. 88 - 93
Detailed information (abstract, keywords, etc)
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R2-4 (Time: 14:46 - 14:48)

Title	A Routing Method Using Minimum Cost Flow Algorithm for Routes with Target Wire Lengths
Author	*Kunihiro Fujiyoshi, Kazuo Yamane (Tokyo Univ. of Agri. and Tech., Japan)
Page	pp. 94 - 99
Detailed information (abstract, keywords, etc)

R2-5 (Time: 14:48 - 14:50)

Title	Compact Pipeline Hardware Architecture for Pattern Matching on Real-Time Traffic Signs Detection
Author	*Anh-Tuan Hoang, Mutsumi Omori, Masaharu Yamamoto, Tetsushi Koide (Hiroshima Univ., Japan)
Page	pp. 100 - 105
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R2-6 (Time: 14:50 - 14:52)

Title	A Parallel Simulated Annealing Algorithm with Look-Ahead Neighbor Solution Generation
Author	*Yusuke Ota, Kazuhito Ito (Saitama Univ., Japan)
Page	pp. 106 - 111
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R2-7s (Time: 14:52 - 14:54)

Title	A 10-Bit Low-Glitch Binary-Weighted Current-Steering DAC
Author	*Fang-Ting Chou, Chung-Chih Hung (National Chiao Tung Univ., Taiwan)
Page	pp. 112 - 113
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R2-8 (Time: 14:54 - 14:56)

Title	Rover II: A Router for Via Configurable Structured ASIC with Standard Cells and IPs
Author	Chiung-Chih Ho, Hsin-Pei Tsai, *Rung-Bin Lin (Yuan Ze Univ., Taiwan)
Page	pp. 114 - 117
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R2-9 (Time: 14:56 - 14:58)

Title	A Compact and Energy-Efficient Muller C-Element for Low-Voltage Asynchronous CMOS Digital Circuits
Author	*Yuzuru Shizuku, Tetsuya Hirose, Yuya Danno, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 118 - 122
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R2-10 (Time: 14:58 - 15:00)

Title	Analytical Thermal Modeling and Calibration Method for Lithium-Ion Batteries
Author	*Keiji Kato, Yusuke Yamamoto, Naoki Kawarabayashi, Lei Lin, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 123 - 128
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R2-11 (Time: 15:00 - 15:02)

Title	A Sensor Modeling Technique Using SystemC-AMS For Fast Simulation of System-in-Package Based Bio-Medical Systems
Author	*Arif Ullah Khan, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Page	pp. 129 - 133
Detailed information (abstract, keywords, etc)
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R2-12 (Time: 15:02 - 15:04)

Title	A Cool Charger for Lithium-Ion Battery
Author	*Yusuke Yamamoto, Keiji Kato, Lei Lin, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 134 - 139
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R2-13s (Time: 15:04 - 15:06)

Title	A Hardware Generator for Aesthetic Nonlinear Filter Banks
Author	*Tomoki Komuro, Hirotaka Nishikawa, Yukihiro Iguchi, Kaoru Arakawa (Meiji Univ., Japan)
Page	pp. 140 - 141
Detailed information (abstract, keywords, etc)
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Keynote Speech II
Time: 15:50 - 16:50 Monday, October 21, 2013
Location: Tanchō-Hakuchō 1
Chair: Nagisa Ishiura (Kwansei Gakuin Univ., Japan)

K2 (Time: 15:50 - 16:50)

Title	Replacing Optical Lenses by Silicon Structures
Author	*Rudy Lauwereins (IMEC, Belgium)
Page	p. 142
Detailed information (abstract, keywords, etc)
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Poster III
Time: 16:50 - 18:00 Monday, October 21, 2013
Location: Tanchō-Hakuchō 1 & Kujyaku
Chairs: Shinobu Nagayama (Hiroshima City Univ., Japan), Zhu Qiang (Cadence Design Systems, Japan)

R3-1 (Time: 16:50 - 16:52)

Title	A Heuristic Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions
Author	Tsutomu Sasao, *Yuta Urano, Yukihiro Iguchi (Meiji Univ., Japan)
Page	pp. 143 - 148
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R3-2 (Time: 16:52 - 16:54)

Title	A New Design Methodology for Rounding and Hardware Minimization in Look-Up-Table-Based Arithmetic Function Evaluation
Author	*Shen-Fu Hsiao (National Sun Yat-sen Univ., Taiwan), Hou-Jen Ko (Purdue Univ., U.S.A.), Yu-Ling Tseng (SpringSoft, Taiwan), Chia-Sheng Wen (National Sun Yat-sen Univ., Taiwan)
Page	pp. 149 - 152
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R3-3 (Time: 16:54 - 16:56)

Title	A Global Router Considering Scenic Controls
Author	Hsueh-Ju Chou (Faraday Technology, Taiwan), Hsi-An Chien, *Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 153 - 158
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R3-4 (Time: 16:56 - 16:58)

Title	A Tuning Method of Programmable Delay Element with Two Values for Yield Improvement
Author	*Hayato Mashiko, Yukihide Kohira (Univ. of Aizu, Japan)
Page	pp. 159 - 164
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R3-5 (Time: 16:58 - 17:00)

Title	Impact of Drive Strength and Well-Contact Density on Heavy-Ion-Induced Single Event Transient
Author	*Jun Furuta (Kyoto Univ., Japan), Masaki Masuda, Katsuyuki Takeuchi, Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan), Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 165 - 169
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R3-6 (Time: 17:00 - 17:02)

Title	A Technique for Accelerating Adaptive Super Resolution Technique Based on Local Features of Images Using GPU
Author	*Kento Kugai, Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 170 - 175
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R3-7 (Time: 17:02 - 17:04)

Title	Parallel Layer-Aware Partitioning for 3D Designs
Author	*Yi-Hang Chen, Yi-Ting Chen, Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Page	pp. 176 - 179
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R3-8 (Time: 17:04 - 17:06)

Title	Lithium-Ion Battery Degradation Model and Its Application to Power Management of Smart House
Author	*Ryosuke Miyahara, Ami Watanabe, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 180 - 185
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R3-9 (Time: 17:06 - 17:08)

Title	Parameter Estimation and Model Reduction for Digital IIR Filters Using a Modified PSO Algorithm
Author	*Wei-Der Chang, Ching-Lung Chi (Shu-Te Univ., Taiwan)
Page	pp. 186 - 189
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R3-10 (Time: 17:08 - 17:10)

Title	Investigating Performance Advantages of Random Topologies on Network-on-Chip
Author	Sarat Yoowattana (Asian Inst. of Tech., Thailand), *Ikki Fujiwara, Michihiro Koibuchi (NII, Japan)
Page	pp. 190 - 194
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R3-11 (Time: 17:10 - 17:12)

Title	Speed Traffic-Sign Recognition Algorithm for Real-Time Driving Assistant System
Author	*Masaharu Yamamoto, Anh-Tuan Hoang, Mutsumi Omori, Tetsushi Koide (Hiroshima Univ., Japan)
Page	pp. 195 - 200
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R3-12s (Time: 17:12 - 17:14)

Title	A Development and Evaluation of Variable Speed Charger System for Lithium-Ion Battery
Author	*Akihiro Segawa, Yusuke Yamamoto, Lei Lin, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 201 - 202
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Tuesday, October 22, 2013

Invited Talk II
Time: 9:00 - 10:00 Tuesday, October 22, 2013
Location: Tanchō-Hakuchō 1
Chair: Nagisa Ishiura (Kwansei Gakuin Univ., Japan)

I2 (Time: 9:00 - 10:00)

Title	Power of Enumeration --- State-of-the-art Algorithms for Tackling Combinatorial Explosion
Author	*Shin-ichi Minato (Hokkaido Univ./JST, Japan)
Page	pp. 203 - 207
Detailed information (abstract, keywords, etc)

Poster IV
Time: 10:00 - 11:30 Tuesday, October 22, 2013
Location: Tanchō-Hakuchō 1 & Kujyaku
Chairs: Masato Inagi (Hiroshima City Univ., Japan), Yukihiro Iguchi (Meiji Univ., Japan)

R4-1 (Time: 10:00 - 10:02)

Title	High Speed Approximation Feature Extraction in CAD System for Colorectal Endoscopic Images with NBI Magnification
Author	*Tsubasa Mishima, Satoshi Shigemi, Anh-Tuan Hoang, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Rie Miyaki, Taiji Matsuo, Shigeto Yoshida, Shinji Tanaka (Hiroshima Univ., Japan)
Page	pp. 208 - 213
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R4-2 (Time: 10:02 - 10:04)

Title	A Fixed-Length Routing Method Based on the Color-Coding Algorithm
Author	*Tieyuan Pan, Yasuhiro Takashima (Univ. of Kitakyushu, Japan)
Page	pp. 214 - 219
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R4-3 (Time: 10:04 - 10:06)

Title	Retiming of Single Flux Quantum Logic Circuits for Flip-Flop Reduction
Author	*Nobutaka Kito (Chukyo Univ., Japan), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ., Japan)
Page	pp. 220 - 225
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R4-4 (Time: 10:06 - 10:08)

Title	Forwarding Unit Generation with Runtime Dependency Analysis in High-Level Synthesis
Author	*Shingo Kusakabe, Kenshu Seto (Tokyo City Univ., Japan)
Page	pp. 226 - 230
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R4-5 (Time: 10:08 - 10:10)

Title	An NFA-Based Programmable Regular Expression Matching Engine Highly Suitable for FPGA Implementation
Author	*Hiroki Takaguchi, Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ., Japan)
Page	pp. 231 - 236
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R4-6 (Time: 10:10 - 10:12)

Title	Graphillion: ZDD-Based Software Library for Very Large Sets of Graphs
Author	Takeru Inoue, *Hiroaki Iwashita (JST, Japan), Jun Kawahara (NAIST, Japan), Shin-ichi Minato (Hokkaido Univ., Japan)
Page	pp. 237 - 242
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R4-7 (Time: 10:12 - 10:14)

Title	Clock Jitter Compensation for Continuous-Time Sigma-Delta Modulator Through Divided-by-N Feedback DAC
Author	*Zong-Yi Chen, Chung-Chih Hung (National Chiao Tung Univ., Taiwan)
Page	pp. 243 - 247
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R4-8 (Time: 10:14 - 10:16)

Title	Simultaneous Escape Routing Considering Length Matching of Differential Pairs
Author	Yen-Jung Lee, *Hung-Ming Chen, Ching-Yu Chin (National Chiao Tung Univ., Taiwan)
Page	pp. 248 - 252
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R4-9 (Time: 10:16 - 10:18)

Title	Technology Remapping Based on Multiple Solutions for Post-Mask Functional ECO
Author	*Yudai Kabata, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 253 - 258
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R4-10s (Time: 10:18 - 10:20)

Title	A Fast Trace-Driven Heterogeneous L1 Cache Configuration Simulator for Dual-Core Processors
Author	*Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ., Japan)
Page	pp. 259 - 260
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R4-11 (Time: 10:20 - 10:22)

Title	A Dynamic Offload Scheduler for Spatial Multitasking on Intel Xeon Phi Coprocessor
Author	*Takamichi Miyamoto, Kazuhisa Ishizaka, Takeo Hosomi (NEC, Japan)
Page	pp. 261 - 266
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R4-12s (Time: 10:22 - 10:24)

Title	A Restricted Dynamically Reconfigurable Architecture for Low Power Processors
Author	*Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ., Japan)
Page	pp. 267 - 268
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R4-13 (Time: 10:24 - 10:26)

Title	A Processor Architecture for Motion Sensing Systems Using Accelerometer
Author	*Takashi Matsuo, Arif Ullah Khan (Osaka Univ., Japan), Takashi Hamabe (MICRONIX, Japan), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Page	pp. 269 - 274
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R4-14 (Time: 10:26 - 10:28)

Title	Radiation-Hard Layout Structures on Bulk and SOI Process by Device-Level Simulations
Author	*Kuiyuan Zhang, Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan)
Page	pp. 275 - 279
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R4-15s (Time: 10:28 - 10:30)

Title	Event Modeling Method for Verification of Power Analysis Attacks
Author	*Kyota Sugioka, Toshiya Asai, Masaya Yoshikawa (Meijo Univ., Japan)
Page	pp. 280 - 281
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R4-16 (Time: 10:30 - 10:32)

Title	A Variable-Length String Matching Circuit Based On SeqBDDs
Author	*Atsushi Matsuo, Yasunori Takagi (Ritsumeikan Univ., Japan), Hiroki Nakahara (Kagoshima Univ., Japan), Shigeru Yamashita (Ritsumeikan Univ., Japan)
Page	pp. 282 - 287
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R4-17s (Time: 10:32 - 10:34)

Title	An Image Compression Method for Frame Memory Size Reduction Using Local Feature of Images
Author	*Yuki Fukuhara (Osaka Univ., Japan), Akihisa Yamada (Sharp/Osaka Univ., Japan), Takao Onoye (Osaka Univ., Japan)
Page	pp. 288 - 289
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Invited Talk III
Time: 13:00 - 14:00 Tuesday, October 22, 2013
Location: Tanchō-Hakuchō 1
Chair: Nagisa Ishiura (Kwansei Gakuin Univ., Japan)

I3 (Time: 13:00 - 14:00)

Title	Physical Design of Microfluidic Biochips
Author	*Tsung-Yi Ho (National Cheng Kung Univ., Taiwan)
Page	p. 290
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Panel Discussion
Time: 14:00 - 15:30 Tuesday, October 22, 2013
Location: Tanchō-Hakuchō 1
Moderator: Masahiro Fujita (Univ. of Tokyo, Japan)

D (Time: 14:00 - 15:30)

Title	Application of EDA Technologies to Non-EDA Areas
Author	Organizer/Moderator: Masahiro Fujita (Univ. of Tokyo, Japan), Panelists: Rudy Lauwereins (IMEC, Belgium), Shin-ichi Minato (Hokkaido Univ., Japan), Tsung-Yi Ho (National Cheng Kung Univ., Taiwan), Giovanni De Micheli (EPFL, Switzerland), Kazutoshi Wakabayashi (NEC, Japan)
Page	p. 291
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Poster V
Time: 15:30 - 17:00 Tuesday, October 22, 2013
Location: Tanchō-Hakuchō 1 & Kujyaku
Chairs: Yuko Hara-Azumi (NAIST, Japan), Masashi Imai (Hirosaki Univ., Japan)

R5-1 (Time: 15:30 - 15:32)

Title	A Study of ESD Clamp Placement Impact on Peripheral- and Area-I/O Designs
Author	*Yi-Cheng Liang, Hung-Ming Chen, Ming-Fang Lai (National Chiao Tung Univ., Taiwan)
Page	pp. 292 - 297
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R5-2 (Time: 15:32 - 15:34)

Title	Customizable Hardware Architecture of Support Vector Machine in CAD System for Colorectal Endoscopic Images with NBI Magnification
Author	*Satoshi Shigemi, Tsubasa Mishima, Anh-Tuan Hoang, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Rie Miyaki, Taiji Matsuo, Shigeto Yoshida, Shinji Tanaka (Hiroshima Univ., Japan)
Page	pp. 298 - 303
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R5-3 (Time: 15:34 - 15:36)

Title	Analysis of Corner Conditions in PVT Variations and Reliability Degradations
Author	Atsushi Kurokawa, *Masayuki Watanabe, Makoto Hoshi, Tetsuya Kobayashi, Masa-aki Fukase (Hirosaki Univ., Japan)
Page	pp. 304 - 309
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R5-4 (Time: 15:36 - 15:38)

Title	High Level Synthesis with Stream Query to C Parser: Eliminating Hardware Development Difficulties for Software Developers
Author	*Eric Shun Fukuda (Hokkaido Univ., Japan), Takashi Takenaka, Hiroaki Inoue (NEC, Japan), Hideyuki Kawashima (Univ. of Tsukuba, Japan), Tetsuya Asai, Masato Motomura (Hokkaido Univ., Japan)
Page	pp. 310 - 315
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R5-5 (Time: 15:38 - 15:40)

Title	Faster Multiple Pattern Matching System on GPU Based on Bit-Parallelism
Author	*Hirohito Sasakawa, Hiroki Arimura (Hokkaido Univ., Japan)
Page	pp. 316 - 321
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R5-6 (Time: 15:40 - 15:42)

Title	High-Level Synthesis for Nested Loop Kernels with Non-Uniform Dependencies
Author	*Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ., Japan)
Page	pp. 322 - 327
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R5-7 (Time: 15:42 - 15:44)

Title	A Fast Simplification Algorithm for Packet Classification
Author	*Infall Syafalni (Kyushu Inst. of Tech., Japan), Tsutomu Sasao (Meiji Univ., Japan)
Page	pp. 328 - 333
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R5-8 (Time: 15:44 - 15:46)

Title	A Low Energy Full TMR Design Method with Optimized Selection of Time/Space TMR Mode and Supply Voltage
Author	*Kazuhito Ito, Yuki Hayashi (Saitama Univ., Japan)
Page	pp. 334 - 339
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R5-9s (Time: 15:46 - 15:48)

Title	Via-Configurable Structured Asic Using Dual Supply Voltages
Author	Ta-Kai Lin (Yuan Ze Univ., Taiwan), Kuen-Wey Lin (National Chiao Tung Univ., Taiwan), Chang-Hao Chiu, *Rung-Bin Lin (Yuan Ze Univ., Taiwan)
Page	pp. 340 - 341
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R5-10 (Time: 15:48 - 15:50)

Title	Automatic On-Chip Interface Synthesis Between Incompatible Protocols with Advanced Features
Author	*Jiayi Zhang, Masahiro Fujita (Univ. of Tokyo, Japan)
Page	pp. 342 - 347
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R5-11 (Time: 15:50 - 15:52)

Title	Low-Power Op-Amp with Capacitor-Base On-Chip Power Supply
Author	*Kazuhiro Hanada, Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)
Page	pp. 348 - 353
Detailed information (abstract, keywords, etc)
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R5-12 (Time: 15:52 - 15:54)

Title	A Basic-Block Level Optimistic Energy Estimation for Power-Gated VLIW Data-Path Model
Author	*Shunsuke Nakamura, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 354 - 359
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R5-13 (Time: 15:54 - 15:56)

Title	A Memory-Saving Technique for 4K Super-Resolution Circuit with Binary Tree Dictionary
Author	*Ayumi Kiriyama, Ryo Matsuzuka, Kohei Michibata, Takahiro Kitayama, Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 360 - 365
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R5-14 (Time: 15:56 - 15:58)

Title	HLS Utilizing Area Optimizing Method for High-Definition MRA-TV Denoise Circuit
Author	*Eita Kobayashi, Kenta Senzaki, Atsufumi Shibayama, Yuichi Nakamura (NEC, Japan)
Page	pp. 366 - 371
Detailed information (abstract, keywords, etc)
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R5-15 (Time: 15:58 - 16:00)

Title	A Circuit Design Method for Dynamic Reconfigurable Circuits
Author	*Hajime Sawano, Takashi Kambe (Kinki Univ., Japan)
Page	pp. 372 - 376
Detailed information (abstract, keywords, etc)
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R5-16 (Time: 16:00 - 16:02)

Title	Concurrent Verification Experience of Cache Protocol in Real Development of Large SMP Server Product by Using Model Checking
Author	*Toru Shonai (Hitachi, Japan), Shoichi Hanaki (OKANO Electric, Japan), Yoshiaki Kinoshita (Hitachi, Japan)
Page	pp. 377 - 382
Detailed information (abstract, keywords, etc)
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R5-17 (Time: 16:02 - 16:04)

Title	Implementation of Strictly Convex QP Solver with Multiple Precision Arithmetic
Author	*Masahiro Kimura, Hiroshige Dan (Kansai Univ., Japan)
Page	pp. 383 - 386
Detailed information (abstract, keywords, etc)

SASIMI 2013 The 18th Workshop on Synthesis And System Integration of Mixed Information Technologies Technical Program

Session Schedule

List of Papers

SASIMI 2013
The 18th Workshop on Synthesis And System Integration of Mixed Information Technologies
Technical Program