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SASIMI 2015
The 19th Workshop on Synthesis And System Integration of Mixed Information Technologies

Poster I
Time: 10:15 - 12:00 Monday, March 16, 2015
Chairs: Ren-Song Tsay (National Tsing Hua Univ., Taiwan), Po-Hung Lin (National Chung Cheng Univ., Taiwan)

R1-1 (Time: 10:15 - 10:17)
TitleMemory Synthesis for Multi-Processor System-on-Chips with Reconfigurable 3D-stacked SRAMs
AuthorMeng-Ling Tsai, *Yi-Jung Chen, Yi-Ting Chen, Ru-Hua Chang (National Chi Nan Univ., Taiwan)
Pagepp. 2 - 7
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R1-2 (Time: 10:17 - 10:19)
TitleThermal-Pattern-Aware Voltage Assignment for Task Scheduler on 3D Multi-Core Processors
AuthorChien-Hui Liao, *Cheng Suo, Charles Hung-Pin Wen (National Chiao Tung Univ., Taiwan)
Pagepp. 8 - 9
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R1-3 (Time: 10:19 - 10:21)
TitleHigh-Level Synthesis from Programs with External Interrupt Handling
Author*Naoya Ito, Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Hiroyuki Tomiyama (Ritsumeikan Univ., Japan), Hiroyuki Kanbara (Advanced Scientific Technology & Management Research Institute of KYOTO, Japan)
Pagepp. 10 - 15
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R1-4 (Time: 10:21 - 10:23)
TitleAn SOC Estimation System for Lithium Ion Batteries Considering Thermal Characteristics
Author*Ryu Ishizaki, Lei Lin, Naoki Kawarabayashi, Masahiro Fukui (Ritsumeikan Univ., Japan)
Pagepp. 16 - 21
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R1-5 (Time: 10:23 - 10:25)
TitleDynamic Data Migration to Eliminate Bank-Level Interference for Stencil Applications in Multicore Systems
AuthorWei-Hen Lo, *Yen-Hao Chen, TingTing Hwang (National Tsing Hua Univ., Taiwan)
Pagepp. 22 - 27
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R1-6 (Time: 10:25 - 10:27)
TitleA Battery Smart Sensor and Its SOC Estimation Function for Assembled Lithium-Ion Batteries
Author*Naoki Kawarabayashi, Lei Lin, Ryu Ishizaki, Masahiro Fukui (Ritsumeikan Univ., Japan), Isao Shirakawa (Univ. of Hyogo, Japan)
Pagepp. 28 - 33
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R1-7 (Time: 10:27 - 10:29)
TitleA Fast and Highly Accurate Statistical Based Model for Performance Estimation of MPSoC On-Chip Bus
Author*Farhan Shafiq, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda (Tokyo Inst. of Tech., Japan)
Pagepp. 34 - 39
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R1-8 (Time: 10:29 - 10:31)
TitleC-Based RTL Design Framework for Processor and Hardware-IP Synthesis
Author*Tsuyoshi Isshiki, Koshiro Date, Daisuke Kugimiya, Dongju Li, Hiroaki Kunieda (Tokyo Inst. of Tech., Japan)
Pagepp. 40 - 45
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R1-9 (Time: 10:31 - 10:33)
TitleProfiler for Control System in System Level Design
Author*Miaw Torng-Der, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ., Japan)
Pagepp. 46 - 51
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R1-10 (Time: 10:33 - 10:35)
TitleSocket-Based Performance Monitoring Tool Suite for System-on-Chips
Author*Ting-Hsuan Wu, Tsun-Hsin Chang, Ing-Jer Huang (National Sun Yat-sen Univ., Taiwan)
Pagepp. 52 - 55
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R1-11 (Time: 10:35 - 10:37)
TitleMinimization of Register Area Cost for Soft-Error Correction in Low Energy DMR Design
Author*Kazuhito Ito, Takumi Negishi (Saitama Univ., Japan)
Pagepp. 56 - 61
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R1-12 (Time: 10:37 - 10:39)
TitleSimultaneous Test Scheduling and TAM Bus Wire Assignment for Core-Based SoC Designs
AuthorTe-Jui Wang, *Ching-Chun Chiu, Shih-Hsu Huang (Chung Yuan Christian Univ., Taiwan)
Pagepp. 62 - 67
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R1-13 (Time: 10:39 - 10:41)
TitleAutomatic Analog Synthesis Platform with Low-Noise Consideration
AuthorYing-Chi Lien, Ching-Mao Lee, Chih-Wei Li, *Yi-Syue Han, Chien-Nan Jimmy Liu (National Central Univ., Taiwan)
Pagepp. 68 - 71
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R1-14 (Time: 10:41 - 10:43)
TitleIntra-Vehicle Network Routing Algorithm for Weight and Wireless Transmit Power Minimization
Author*Ta-Yang Huang, Chia-Jui Chang (National Cheng Kung Univ., Taiwan), Chung-Wei Lin (Univ. of California, Berkeley, U.S.A.), Sudip Roy (National Cheng Kung Univ., Taiwan), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan)
Pagepp. 72 - 77
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R1-15 (Time: 10:43 - 10:45)
TitleAn Automated Flow Integration to Help Analog Layout Design Migration
AuthorJou-Chun Lin, *Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Pagepp. 78 - 82
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R1-16 (Time: 10:45 - 10:47)
TitleRip-Up and Reroute Based Routing Algorithm for Self-Aligned Double Patterning
Author*Takeshi Ihara, Atsushi Takahashi (Tokyo Inst. of Tech., Japan), Chikaaki Kodama (Toshiba, Japan)
Pagepp. 83 - 88
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R1-17 (Time: 10:47 - 10:49)
TitleAnalysis of the Distance Dependent Multiple Cell Upset Rates on 65-nm Redundant Latches by a PHITS-TCAD Simulation System
Author*Kuiyuan Zhang, Jun Furuta, Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan)
Pagepp. 89 - 93
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R1-18 (Time: 10:49 - 10:51)
TitleFeasible Shortest Path Frame Bounded Maze-Routing Algorithm for ML-OARST with Ripping up and Re-Building Steiner Points
Author*Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li (National Chiao Tung Univ., Taiwan), Rung-Bin Lin (Yuan Ze Univ., Taiwan)
Pagepp. 94 - 99
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R1-19 (Time: 10:51 - 10:53)
TitleA TPL-Friendly Legalizer for Standard Cell Based Design
Author*Hsiu-Yu Lai, Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Pagepp. 100 - 105
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R1-20 (Time: 10:53 - 10:55)
TitleGranularity of Via Configurable Logic Block for Structured ASIC
AuthorHui-Hsiang Tung (Oriental Inst. of Tech., Taiwan), *Rung-Bin Lin (Yuan Ze Univ., Taiwan)
Pagepp. 106 - 110
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R1-21 (Time: 10:55 - 10:57)
TitleOn the Impact of Initial Placement to SA-Based Placement for Mixed-Grained Reconfigurable Architecture
Author*Takashi Kishimoto, Hiroyuki Ochi (Ritsumeikan Univ., Japan)
Pagepp. 111 - 116
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