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SASIMI 2015
The 19th Workshop on Synthesis And System Integration of Mixed Information Technologies

Poster III
Time: 9:45 - 11:30 Tuesday, March 17, 2015
Chairs: Kazuhito Ito (Saitama Univ., Japan), Shigeru Yamashita (Ritsumeikan Univ., Japan)

R3-1 (Time: 9:45 - 9:47)
TitleNew nMOS Dynamic Shift Registers for Driver Circuit of Small LCDs and Their Evaluations
Author*Shinji Higa, Shuji Tsukiyama (Chuo Univ., Japan), Isao Shirakawa (Univ. of Hyogo, Japan)
Pagepp. 218 - 223
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R3-2 (Time: 9:47 - 9:49)
TitleA Floorplan-Driven High-Level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs
Author*Koichi Fujiwara, Masao Yanagisawa, Nozomu Togawa (Waseda Univ., Japan)
Pagepp. 224 - 225
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R3-3 (Time: 9:49 - 9:51)
TitleIntroducing Loop Statements in Random Testing of C Compilers Based on Expected Value Calculation
Author*Kazuhiro Nakamura, Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
Pagepp. 226 - 227
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R3-4 (Time: 9:51 - 9:53)
TitleProduct Term Minimization in ROBDDs with Application to Reconfigurable SET Array Synthesis
Author*Yi-Hang Chen, Yang Chen, Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Pagepp. 228 - 231
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R3-5 (Time: 9:53 - 9:55)
TitleAn Effective Timing-Coherent Transactor Generation Approach for Mixed-Level System Simulations
Author*Hsin-I Wu, Li-chun Chen, Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Pagepp. 232 - 237
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R3-6 (Time: 9:55 - 9:57)
TitleAn Accurate Processor Power Estimation Approach Based on Microcomponent Structure Analysis
Author*Chi-Kang Chen, Zih-Ci Huang, Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Pagepp. 238 - 243
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R3-7 (Time: 9:57 - 9:59)
TitleA Verilog Compiler Proposal for VerCPU Simulator
Author*Tze Sin Tan (Altera, Malaysia), Bakhtiar Affendi Rosdi (Univ. Sains Malaysia, Malaysia)
Pagepp. 244 - 249
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R3-8 (Time: 9:59 - 10:01)
TitleMorFPGA Duo: A Dual-Core FPGA-Based Embedded System Development Platform
AuthorChih-Chyau Yang, *Chun-Yu Chen, Chun-Wen Cheng, Yi-Jun Liu, Chien-Ming Wu, Chun-Ming Huang (National Chip Implementation Center, Taiwan)
Pagepp. 250 - 254
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R3-9 (Time: 10:01 - 10:03)
TitleA 3G-Based Bridge Structural Health Monitoring System Using Cost-Effective 1-Axis Accelerometers
AuthorChih-Hsing Lin, *Wen-Ching Chen, Chih-Ting Kuo, Gang-Neng Sung, Chih-Chyau Yang, Chien-Ming Wu, Chun-Ming Huang (National Chip Implementation Center, Taiwan)
Pagepp. 255 - 259
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R3-10 (Time: 10:03 - 10:05)
TitleAnalytical Reliability Model of Die-Stacked DRAM Protected by Error Control Code and TSV Fault Tolerant Coding Technique
Author*Tadayuki Matsumura, Tsuyoshi Tanaka (Hitachi, Japan)
Pagepp. 260 - 265
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R3-11 (Time: 10:05 - 10:07)
TitleProtection Method for AES IP Core from Scan-Based Attack
Author*Yifan Wu, Shinji Kimura (Waseda Univ., Japan)
Pagepp. 266 - 271
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R3-12 (Time: 10:07 - 10:09)
TitleSoft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing in Triple Algorithm Redundancy
Author*Junghoon Oh, Mineo Kaneko (JAIST, Japan)
Pagepp. 272 - 277
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R3-13 (Time: 10:09 - 10:11)
TitleUsing Range-Equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking
AuthorYung-Chih Chen (Yuan Ze Univ., Taiwan), Wei-An Ji, Chih-Chung Wang, *Ching-Yi Huang, Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Pagepp. 278 - 282
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R3-14 (Time: 10:11 - 10:13)
TitleDesign of PPG-Based Heart Rate Sensor Enabling Motion Artifact Cancellation
Author*Takunori Shimazaki, Shinsuke Hara (Osaka City Univ., Japan)
Pagepp. 283 - 286
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R3-15 (Time: 10:13 - 10:15)
TitleA Redundant Task Allocation Method for Reliable Network-on-Chips
Author*Hiroshi Saito (Univ. of Aizu, Japan), Tomohiro Yoneda (NII, Japan), Yuichi Nakamura (NEC, Japan)
Pagepp. 287 - 292
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R3-16 (Time: 10:15 - 10:17)
TitleSingle-Flux-Quantum Digital Circuit Design Using Clockless Logic Cells with a Jitter Constraint
Author*Ryohei Matsumoto, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Pagepp. 293 - 298
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R3-17 (Time: 10:17 - 10:19)
TitleTime Analysis of Applying Back Gate Bias for Reconfigurable Architectures with SOTB MOSFET
Author*Hayate Okuhara, Hideharu Amano (Keio Univ., Japan)
Pagepp. 299 - 304
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R3-18 (Time: 10:19 - 10:21)
TitleA Cooling Effect Formulation and Implementation of a Cooling System for Li-Ion Battery Modules
Author*Yuki Kitagawa, Yusuke Yamamoto, Masahiro Fukui (Ritsumeikan Univ., Japan)
Pagepp. 305 - 310
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R3-19 (Time: 10:21 - 10:23)
TitleGlobal Transformation-Based Optimization of Threshold Logic Circuits
Author*Maiko Kabu, Takayuki Kasugai, Shigeru Yamashita (Ritsumeikan Univ., Japan), Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Pagepp. 311 - 316
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R3-20 (Time: 10:23 - 10:25)
TitleCounter-Based Victim Cache Hit Rate Optimization
Author*Li-Yen Chang, Chen-Hua Suo, Yi-Yu Liu (Yuan Ze Univ., Taiwan)
Pagepp. 317 - 318
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R3-21 (Time: 10:25 - 10:27)
TitleAn ECO-Friendly Design Style Based on Reconfigurable Cells
Author*Yudai Kabata, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 319 - 324
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