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SASIMI 2015
The 19th Workshop on Synthesis And System Integration of Mixed Information Technologies

Poster IV
Time: 14:55 - 16:40 Tuesday, March 17, 2015
Chairs: Atsushi Takahashi (Tokyo Inst. of Tech., Japan), Ing-Jer Huang (National Sun Yat-sen Univ., Taiwan)

R4-1 (Time: 14:55 - 14:57)
TitleLayout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults - from Device to Circuit Level
AuthorHsuan-Ming Huang, *Yi-Wu Liu, Charles H.-P. Wen (National Chiao Tung Univ., Taiwan)
Pagepp. 327 - 332
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R4-2 (Time: 14:57 - 14:59)
TitleUsing Body Biasing for Energy Efficient Frequency Scaling in a Dynamically Reconfigurable Processor
Author*Johannes Maximilian Kühn (Univ. of Tübingen, Germany), Hideharu Amano (Keio Univ., Japan), Wolfgang Rosenstiel (Univ. of Tübingen, Germany)
Pagepp. 333 - 338
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R4-3 (Time: 14:59 - 15:01)
TitleLow-Power Gated Clock Tree Synthesis for 3D ICs
Author*Yu-Chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin (National Chung Cheng Univ., Taiwan)
Pagepp. 339 - 343
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R4-4 (Time: 15:01 - 15:03)
TitleGraph-Covering-Based Architectural Synthesis for Programmable Digital Microfluidic Biochips
Author*Daiki Kitagawa, Dieu Quang Nguyen, Trung Anh Dinh, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Pagepp. 344 - 349
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R4-5 (Time: 15:03 - 15:05)
TitleContamination-Aware Routing Flow for Both Functional and Washing Droplets in Digital Microfluidic Biochips
Author*Qin Wang, Yiren Shen, Hailong Yao (Tsinghua Univ., China), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan), Yici Cai (Tsinghua Univ., China)
Pagepp. 350 - 355
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R4-6 (Time: 15:05 - 15:07)
TitleObstacle-Avoiding Wind Turbine Placement for Power-Loss and Wake-Effect Optimization
Author*Yu-Wei Wu (National Cheng Kung Univ., Taiwan), Yi-Yu Shi (Missouri Univ. of Science and Tech., U.S.A.), Sudip Roy (National Cheng Kung Univ., Taiwan), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan)
Pagepp. 356 - 361
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R4-7 (Time: 15:07 - 15:09)
TitleAccelerating Random-Walk-Based Power Grid Analysis through Error Smoothing
Author*Tsuyoshi Okazaki, Masayuki Hiromoto, Takashi Sato (Kyoto Univ., Japan)
Pagepp. 362 - 367
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R4-8 (Time: 15:09 - 15:11)
TitleImprovement of Simulated Annealing Search ---Based on Tree Representations---
Author*Takaaki Banno, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan)
Pagepp. 368 - 373
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R4-9 (Time: 15:11 - 15:13)
TitleA Hierarchical Type Segmentation Algorithm Based on Support Vector Machine for Colorectal Endoscopic Images with NBI Magnification
Author*Takumi Okamoto, Tetsushi Koide, Anh-Tuan Hoang, Koki Sugi, Tatsuya Shimizu, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka (Hiroshima Univ., Japan)
Pagepp. 374 - 379
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R4-10 (Time: 15:13 - 15:15)
TitleHigh Performance Feature Transformation Architecture Based on Bag-of-Features in CAD System for Colorectal Endoscopic Images
Author*Koki Sugi, Tetsushi Koide, Anh-Tuan Hoang, Takumi Okamoto, Tatsuya Shimizu, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka (Hiroshima Univ., Japan)
Pagepp. 380 - 385
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R4-11 (Time: 15:15 - 15:17)
TitleHardware Implementation of Motion Estimation Technology Using High Level Synthesis and Investigations into Techniques for Improvements
Author*Shota Nagai, Takashi Kambe (Kindai Univ., Japan), Gen Fujita (Osaka Electro-Communication Univ., Japan)
Pagepp. 386 - 390
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R4-12 (Time: 15:17 - 15:19)
TitleFPGA Oriented Intra Angular Prediction Image Generation Hardware for HEVC Video Coding
Author*Eita Kobayashi, Seiya Shibata, Noriaki Suzuki, Atsufumi Shibayama, Takeo Hosomi (NEC, Japan)
Pagepp. 391 - 396
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R4-13 (Time: 15:19 - 15:21)
TitleHigh Accuracy and Simple Real-Time Circle Detection on Low-Cost FPGA for Traffic-Sign Recognition on Advanced Driver Assistance System
Author*Anh-Tuan Hoang, Masaharu Yamamoto, Tetsushi Koide (Hiroshima Univ., Japan)
Pagepp. 397 - 402
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R4-14 (Time: 15:21 - 15:23)
TitleDMATP: A Design Method and Architecture of TU Parallel Processing for 4K HEVC Hardware Encoder
Author*Seiya Shibata, Eita Kobayashi, Noriaki Suzuki, Atsufumi Shibayama, Takeo Hosomi (NEC, Japan)
Pagepp. 403 - 408
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R4-15 (Time: 15:23 - 15:25)
TitleAn Improved Rate-Distortion Optimized Quantization Algorithm and Its Hardware Implementation
Author*Genki Moriguchi, Takashi Kambe (Kindai Univ., Japan), Gen Fujita (Osaka Electro-Communication Univ., Japan)
Pagepp. 409 - 414
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R4-16 (Time: 15:25 - 15:27)
TitleImplementation and Evaluation of AES/ADPCM on STP and FPGA with High-Level Synthesis
Author*Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ., Japan)
Pagepp. 415 - 420
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R4-17 (Time: 15:27 - 15:29)
TitleSpeed Traffic-Sign Number Recognition on Low Cost FPGA for Robust Sign Distortion and Illumination Conditions
Author*Masaharu Yamamoto, Anh-Tuan Hoang, Tetsushi Koide (Hiroshima Univ., Japan)
Pagepp. 421 - 426
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R4-18 (Time: 15:29 - 15:31)
TitleEfficient Manipulation of Truth Tables on CUDA for Gate-Level Simulation
Author*Yuri Ardila, Tatsuyuki Kida, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Pagepp. 427 - 432
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R4-19 (Time: 15:31 - 15:33)
TitleScan-Based Side-Channel Attack Implementation Evaluation on the LED Cipher Using SASEBO-GII
Author*Huiqian Jiang, Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa (Waseda Univ., Japan)
Pagepp. 433 - 434
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R4-20 (Time: 15:33 - 15:35)
TitleA Study on Visualization of Auscultation-Based Blood Pressure Measurement
Author*Yusuke Katsuki, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)
Pagepp. 435 - 436
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