Invited Talk I
13:40–14:40, Monday, October 24, 2022
Utilization of Dominant Time Constant Information to Improve the Efficiency of Power and Hard-Breakdown Device Simulation
Shigetaka Kumashiro
Kyoto Lab for a Greener Future, Kyoto Institute of Technology
Abstract
Dominant time constants of the response of the linearized semiconductor device equations (Poisson, electron and hole current continuity) are extracted by using Arnoldi method. A new accurate metric for the time step control in the transient device simulation has been derived based on the dominant time constant information. By using this metric, CPU-time of the transient simulation of a power DMOSFET decreases down to 27 % of that by the conventional method. It has been found that Newton iteration diverges if a negative time constant appears during the hard-breakdown simulation of a PN junction. Stable convergence is obtained either by restricting the terminal voltage increment so small that no negative time constant should appear, or by switching to transient simulation upon detecting the appearance of a negative time constant. These two methods are more efficient than the conventional blind-trial-and-error type convergence control method.
Biography
Shigetaka Kumashiro received the B.E. and M.E. degrees from the University of Tokyo, Tokyo, Japan, in 1981 and 1983, respectively, and the Ph.D. degree from Carnegie Mellon University, Pittsburgh, PA, USA, in 1992.
He was with NEC Corporation, Tokyo, from 1983 to 2002, NEC Electronics Corporation, Tokyo, from 2002 to 2010. He has been with Renesas Electronics Corporation, Tokyo, since 2010, where he is currently a Principal EDA Engineer. He was also with STARC, Yokohama, Japan and MIRAI-Selete, Tsukuba, Japan. He also worked for Kyoto Institute of Technology, Kyoto, Japan as a Research Professor from 2016 to 2021 and has been working as a Senior Fellow since 2021.
His current research interests include modeling, simulation, and reliability of ULSI processes and devices.
Dr. Kumashiro is a recipient of the ASP-DAC Best Paper Award in 2001.
He is a senior member of IEEE and a member of IEICE and JSAP.