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SASIMI 2012
The 17th Workshop on Synthesis And System Integration of Mixed Information Technologies

Poster IV
Time: 14:15 - 16:00 Friday, March 9, 2012
Location: Int'l Conf. Room & Mtg. Room 31
Chairs: Chikaaki Kodama (Toshiba Corp., Japan), Keishi Sakanushi (Osaka Univ., Japan)

R4-1
TitleDesign Automation for Digital Microfluidic Biochips: From Fluidic-Level Toward Chip-Level
AuthorTsung-Wei Huang, *Tsung-Yi Ho (National Cheng Kung Univ., Taiwan)
Pagepp. 439 - 444
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R4-2
TitleTiming-Aware Clock Gating Algorithm for Pulse-Latch Circuits
Author*Zong-Han Yang, Tsung-Yi Ho (National Cheng Kung Univ., Taiwan)
Pagepp. 445 - 450
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R4-3
TitleResistivity-based Modeling of Substrate Non-uniformity for Resistance Extraction of Low-Resistivity Substrate
Author*Yasuhiro Ogasahara, Toshiki Kanamoto (Renesas Electronics Corp., Japan), Hisato Inaba, Toshiharu Chiba (Renesas Design Corp., Japan)
Pagepp. 451 - 456
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R4-4
TitleTemperature-Constrained Fixed-Outline Floorplanning for 3D ICs
AuthorCiao-Yu Hong, Wai-Kei Mak, *Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Pagepp. 457 - 459
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R4-5
TitleA GPGPU Implementation of Parallel Backward Euler Algorithm for Power Grid Circuit Simulation
AuthorLei Lin, *Hayato Shiono, Makoto Yokota, Masahiro Fukui (Ritsumeikan Univ., Japan)
Pagepp. 460 - 465
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R4-6s
TitleA Third Order Delta-Sigma Modulator with Shared Opamp Technique for Wireless Applications
Author*Ghazal Fahmy, Daisuke Kanemoto, Haruichi Kanaya, Ramesh Pokharel, Keiji Yoshida (Kyushu Univ., Japan)
Pagepp. 466 - 467
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R4-7s
TitleA Self-Organization Maps Approach to FPGA Placement
AuthorMotoki Amagasaki, *Yasuaki Tomonari, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ., Japan)
Pagepp. 468 - 469
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R4-8
TitleThe Development of CAD System for Via Programmable Structured ASIC VPEX3
Author*Ryohei Hori (Ritsumeikan Univ., Japan), Masaya Yoshikawa (Meijo Univ., Japan), Takeshi Fujino (Ritsumeikan Univ., Japan)
Pagepp. 470 - 475
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R4-9
TitleDesign of Low-Voltage High-Precision Complex Quadrature Modulators
Author*Takahiro Tsushima, Tsuneo Tsukahara (Univ. of Aizu, Japan)
Pagepp. 476 - 481
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R4-10s
TitleA Design of 2GHz Band O-QPSK Wireless Transmitter using 0.18µmCMOS Technology
Author*Yuki Mitani, Nobuhiko Nakano (Keio Univ., Japan)
Pagepp. 482 - 483
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R4-11
TitleA 0.5V PWM-Driven Analog Differential Amplifier Using Subthreshold Leakage Current
Author*Tomochika Harada, Ryuuya Otaki (Yamagata Univ., Japan)
Pagepp. 484 - 487
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R4-12s
Title16PE 3D-Mesh NOC Based 3D Multicore Design and Implementation
AuthorMohamad Hairol Jabbar (ENSTA ParisTech, France), Dominique Houzet (GIPSA-LAB, France), *Omar Hammami (ENSTA ParisTech, France)
Pagepp. 488 - 489
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R4-13s
TitleA Performance Improvement for Floating-Point Arithmetic Unit with Precision Degradation Detection
Author*Soseki Aniya, Toshiaki Kitamura (Hiroshima City Univ., Japan)
Pagepp. 490 - 491
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R4-14
TitleHardware Architecture for Real-Time Operation of Learning-Based Super-Resolution Using Binary Search Tree
Author*Takahiro Kitayama, Kohei Michibata, Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 492 - 496
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R4-15
TitleArchitecture Optimization of Group Signature Circuits for Cloud Computing Environment
Author*Sumio Morioka, Jun Furukawa, Yuichi Nakamura, Kazue Sako (NEC Corp., Japan)
Pagepp. 497 - 502
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R4-16
TitleEfficient Packet Transmission Priority Control Method for Network-on-Chip
Author*Yusuke Sekihara, Takashi Aoki, Akira Onozawa (NTT, Japan)
Pagepp. 503 - 507
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R4-17s
TitleDirect Memory Access Transfer Method with Chaining for Inter-Chip Network
Author*Eiichi Sasaki, Daisuke Sasaki, Ikan Wang, Yusuke Koizumi, Hideharu Amano (Keio Univ., Japan)
Pagepp. 508 - 509
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R4-18
TitleEfficient Barrier Synchronization for 2D Meshed NoC-based Many-core Processors
Author*Lovic Gauthier, Farhad Mehdipour, Koji Inoue, Shinya Ueno, Hiroshi Sasaki (Kyushu Univ., Japan)
Pagepp. 510 - 515
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R4-19
TitleEffective Distributed Parallel Scheduling Methodology for Mobile Cloud Computing
Author*Hiromasa Yamauchi, Koji Kurihara, Toshiya Otomo (Fujitsu Laboratories Ltd., Japan), Yuta Teranishi (Fujitsu Kyushu Network Technologies Ltd., Japan), Takahisa Suzuki, Koichiro Yamashita (Fujitsu Laboratories Ltd., Japan)
Pagepp. 516 - 521
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R4-20
TitleExtending Intent in Android for Distributed Collaboration Framework
Author*Takahiro Ito, Takuya Azumi, Nobuhiko Nishio (Ritsumeikan Univ., Japan)
Pagepp. 522 - 527
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R4-21
TitleEnergy Efficient Instruction-set Extension Considering Inline Expansion
Author*Sho Ninomiya, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Pagepp. 528 - 533
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R4-22
TitleReduction of Glitches for Low-Power Multipliers Using 4-2 Compressors Based on Hybrid-CMOS Logic Style
Author*Yang-uk Son, Yuzuru Shizuku, Takeshi Kogure, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 534 - 538
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R4-23
TitleAffine Transformations of Logic Functions and Their Application to Affine Decompositions of Index Generation Functions
Author*Tsutomu Sasao, Masao Maeta (Kyushu Inst. of Tech., Japan), Radomir Stankovic (Univ. of Nis, Serbia), Stanislav Stankovic (Tampere Univ. of Tech., Finland)
Pagepp. 539 - 543
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R4-24
TitleAn Error Diagnosis Technique Based on SAT Solver
Author*Tomoki Matsuyama, Hiroto Senzaki, Kosuke Watanabe, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 544 - 548
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R4-25
TitlePerformance Evaluation of Various Configuration of Adder in Variable Latency Circuits with Error Detection/Correction Mechanism
Author*Kenta Ando, Atsushi Takahashi (Osaka Univ., Japan)
Pagepp. 549 - 554
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R4-26
TitleA Delay Control Technique for Extremely Low-Voltage Subthreshold CMOS Digital Circuits
Author*Seiichiro Shiga, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 555 - 559
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