SASIMI 2015
The 19th Workshop on Synthesis And System Integration of Mixed Information Technologies
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Monday, March 16, 2015


Registration 8:00 -
Opening 8:40 - 9:00
K1 Keynote Speech I 9:00 - 10:00
Coffee Break 10:00 - 10:15
R1 Poster I 10:15 - 12:00
Lunch 12:00 - 13:30
I1 Invited Talk I 13:30 - 14:20
D Panel Discussion 14:20 - 15:50
Coffee Break 15:50 - 16:10
R2 Poster II 16:10 - 17:55
Banquet 18:30 - 20:30

Tuesday, March 17, 2015


K2 Keynote Speech II 8:30 - 9:30
Coffee Break 9:30 - 9:45
R3 Poster III 9:45 - 11:30
Lunch Break 11:30 - 13:00
I2 Invited Talk II 13:00 - 13:50
Coffee Break 13:50 - 14:05
I3 Invited Talk III 14:05 - 14:55
R4 Poster IV 14:55 - 16:40
Closing 16:40 - 16:50

List of papers

Remark: The presenter of each paper is marked with "*".

Monday, March 16, 2015

Keynote Speech I
Time: 9:00 - 10:00 Monday, March 16, 2015
Chair: Ting-Chi Wang (National Tsing Hua Univ., Taiwan)

K1-1 (Time: 9:00 - 10:00)

Title	Influence of Emerging Devices in Revitalizing Electronic Systems Design
Author	Vijaykrishnan Narayanan (Pennsylvania State Univ., U.S.A.)
Page	p. 1
Detailed information (abstract, keywords, etc)
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Poster I
Time: 10:15 - 12:00 Monday, March 16, 2015
Chairs: Ren-Song Tsay (National Tsing Hua Univ., Taiwan), Po-Hung Lin (National Chung Cheng Univ., Taiwan)

R1-1 (Time: 10:15 - 10:17)

Title	Memory Synthesis for Multi-Processor System-on-Chips with Reconfigurable 3D-stacked SRAMs
Author	Meng-Ling Tsai, *Yi-Jung Chen, Yi-Ting Chen, Ru-Hua Chang (National Chi Nan Univ., Taiwan)
Page	pp. 2 - 7
Detailed information (abstract, keywords, etc)

R1-2 (Time: 10:17 - 10:19)

Title	Thermal-Pattern-Aware Voltage Assignment for Task Scheduler on 3D Multi-Core Processors
Author	Chien-Hui Liao, *Cheng Suo, Charles Hung-Pin Wen (National Chiao Tung Univ., Taiwan)
Page	pp. 8 - 9
Detailed information (abstract, keywords, etc)

R1-3 (Time: 10:19 - 10:21)

Title	High-Level Synthesis from Programs with External Interrupt Handling
Author	*Naoya Ito, Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Hiroyuki Tomiyama (Ritsumeikan Univ., Japan), Hiroyuki Kanbara (Advanced Scientific Technology & Management Research Institute of KYOTO, Japan)
Page	pp. 10 - 15
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R1-4 (Time: 10:21 - 10:23)

Title	An SOC Estimation System for Lithium Ion Batteries Considering Thermal Characteristics
Author	*Ryu Ishizaki, Lei Lin, Naoki Kawarabayashi, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 16 - 21
Detailed information (abstract, keywords, etc)
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R1-5 (Time: 10:23 - 10:25)

Title	Dynamic Data Migration to Eliminate Bank-Level Interference for Stencil Applications in Multicore Systems
Author	Wei-Hen Lo, *Yen-Hao Chen, TingTing Hwang (National Tsing Hua Univ., Taiwan)
Page	pp. 22 - 27
Detailed information (abstract, keywords, etc)
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R1-6 (Time: 10:25 - 10:27)

Title	A Battery Smart Sensor and Its SOC Estimation Function for Assembled Lithium-Ion Batteries
Author	*Naoki Kawarabayashi, Lei Lin, Ryu Ishizaki, Masahiro Fukui (Ritsumeikan Univ., Japan), Isao Shirakawa (Univ. of Hyogo, Japan)
Page	pp. 28 - 33
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R1-7 (Time: 10:27 - 10:29)

Title	A Fast and Highly Accurate Statistical Based Model for Performance Estimation of MPSoC On-Chip Bus
Author	*Farhan Shafiq, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda (Tokyo Inst. of Tech., Japan)
Page	pp. 34 - 39
Detailed information (abstract, keywords, etc)
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R1-8 (Time: 10:29 - 10:31)

Title	C-Based RTL Design Framework for Processor and Hardware-IP Synthesis
Author	*Tsuyoshi Isshiki, Koshiro Date, Daisuke Kugimiya, Dongju Li, Hiroaki Kunieda (Tokyo Inst. of Tech., Japan)
Page	pp. 40 - 45
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R1-9 (Time: 10:31 - 10:33)

Title	Profiler for Control System in System Level Design
Author	*Miaw Torng-Der, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ., Japan)
Page	pp. 46 - 51
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R1-10 (Time: 10:33 - 10:35)

Title	Socket-Based Performance Monitoring Tool Suite for System-on-Chips
Author	*Ting-Hsuan Wu, Tsun-Hsin Chang, Ing-Jer Huang (National Sun Yat-sen Univ., Taiwan)
Page	pp. 52 - 55
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R1-11 (Time: 10:35 - 10:37)

Title	Minimization of Register Area Cost for Soft-Error Correction in Low Energy DMR Design
Author	*Kazuhito Ito, Takumi Negishi (Saitama Univ., Japan)
Page	pp. 56 - 61
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R1-12 (Time: 10:37 - 10:39)

Title	Simultaneous Test Scheduling and TAM Bus Wire Assignment for Core-Based SoC Designs
Author	Te-Jui Wang, *Ching-Chun Chiu, Shih-Hsu Huang (Chung Yuan Christian Univ., Taiwan)
Page	pp. 62 - 67
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R1-13 (Time: 10:39 - 10:41)

Title	Automatic Analog Synthesis Platform with Low-Noise Consideration
Author	Ying-Chi Lien, Ching-Mao Lee, Chih-Wei Li, *Yi-Syue Han, Chien-Nan Jimmy Liu (National Central Univ., Taiwan)
Page	pp. 68 - 71
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R1-14 (Time: 10:41 - 10:43)

Title	Intra-Vehicle Network Routing Algorithm for Weight and Wireless Transmit Power Minimization
Author	*Ta-Yang Huang, Chia-Jui Chang (National Cheng Kung Univ., Taiwan), Chung-Wei Lin (Univ. of California, Berkeley, U.S.A.), Sudip Roy (National Cheng Kung Univ., Taiwan), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan)
Page	pp. 72 - 77
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R1-15 (Time: 10:43 - 10:45)

Title	An Automated Flow Integration to Help Analog Layout Design Migration
Author	Jou-Chun Lin, *Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Page	pp. 78 - 82
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R1-16 (Time: 10:45 - 10:47)

Title	Rip-Up and Reroute Based Routing Algorithm for Self-Aligned Double Patterning
Author	*Takeshi Ihara, Atsushi Takahashi (Tokyo Inst. of Tech., Japan), Chikaaki Kodama (Toshiba, Japan)
Page	pp. 83 - 88
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R1-17 (Time: 10:47 - 10:49)

Title	Analysis of the Distance Dependent Multiple Cell Upset Rates on 65-nm Redundant Latches by a PHITS-TCAD Simulation System
Author	*Kuiyuan Zhang, Jun Furuta, Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan)
Page	pp. 89 - 93
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R1-18 (Time: 10:49 - 10:51)

Title	Feasible Shortest Path Frame Bounded Maze-Routing Algorithm for ML-OARST with Ripping up and Re-Building Steiner Points
Author	*Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li (National Chiao Tung Univ., Taiwan), Rung-Bin Lin (Yuan Ze Univ., Taiwan)
Page	pp. 94 - 99
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R1-19 (Time: 10:51 - 10:53)

Title	A TPL-Friendly Legalizer for Standard Cell Based Design
Author	*Hsiu-Yu Lai, Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 100 - 105
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R1-20 (Time: 10:53 - 10:55)

Title	Granularity of Via Configurable Logic Block for Structured ASIC
Author	Hui-Hsiang Tung (Oriental Inst. of Tech., Taiwan), *Rung-Bin Lin (Yuan Ze Univ., Taiwan)
Page	pp. 106 - 110
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R1-21 (Time: 10:55 - 10:57)

Title	On the Impact of Initial Placement to SA-Based Placement for Mixed-Grained Reconfigurable Architecture
Author	*Takashi Kishimoto, Hiroyuki Ochi (Ritsumeikan Univ., Japan)
Page	pp. 111 - 116
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Invited Talk I
Time: 13:30 - 14:20 Monday, March 16, 2015
Chair: Tsung-Yi Ho (National Chiao Tung Univ., Taiwan)

I1-1 (Time: 13:30 - 14:20)

Title	Through-Silicon-Via Inductor based DC-DC Converters: The Marriage of the Princess and the Dragon
Author	*Yiyu Shi (Missouri Univ. of Science and Tech., U.S.A.)
Page	p. 117
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Panel Discussion
Time: 14:20 - 15:50 Monday, March 16, 2015
Moderator: Ing-Chao Lin (National Cheng Kung Univ., Taiwan)

D-1 (Time: 14:20 - 14:22)

Title	Circuit Reliability: Major Roadblock in Future Technology?
Author	Organizer: Tsung-Yi Ho (National Chiao Tung Univ., Taiwan), Moderator: Ing-Chao Lin (National Cheng Kung Univ., Taiwan), Panelists: Vijaykrishnan Narayanan (Pennsylvania State Univ., U.S.A.), Anthony Oates (TSMC, Taiwan), Ulf Schlichtmann (Tech. Univ. München, Germany), Yiyu Shi (Missouri Univ. of Science and Tech., U.S.A.), Tomohiro Yoneda (NII, Japan)
Page	p. 118
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Poster II
Time: 16:10 - 17:55 Monday, March 16, 2015
Chairs: Eita Kobayashi (NEC, Japan), Chun-Yao Wang (National Tsing Hua Univ., Taiwan)

R2-1 (Time: 16:10 - 16:12)

Title	Fast Transient and High Current Efficiency Voltage Regulator with Hybrid Dynamic Biasing Technique
Author	Chia-Min Chen, *Yen-Wei Liu, Chung-Chih Hung (National Chiao Tung Univ., Taiwan)
Page	pp. 119 - 122
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R2-2 (Time: 16:12 - 16:14)

Title	A BIST Scheme Detecting Catastrophic Faults of MOSFETs in Bandgap Reference with Self-Biased Operational Amplifier
Author	*Takuya Bando, Masayoshi Tachibana (Kochi Univ. of Tech., Japan)
Page	pp. 123 - 127
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R2-3 (Time: 16:14 - 16:16)

Title	Scan Test of Latch-Based Asynchronous Pipeline Circuits under 2-Phase Handshaking Protocol
Author	*Kyohei Terayama, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ., Japan)
Page	pp. 128 - 133
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R2-4 (Time: 16:16 - 16:18)

Title	Data Reduction and Parallelization for Human Detection System
Author	*Mao Hatto, Takaaki Miyajima, Hideharu Amano (Keio Univ., Japan)
Page	pp. 134 - 139
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R2-5 (Time: 16:18 - 16:20)

Title	Evaluation of Approximate SAD Circuits with Error Compensation
Author	*Toshihiro Goto, Yasunori Takagi, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Page	pp. 140 - 145
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R2-6 (Time: 16:20 - 16:22)

Title	A Circuit Implementable 5-Output nMOSFET Shearing Stress Sensor
Author	*Tomochika Harada, Kousuke Takeuchi (Yamagata Univ., Japan)
Page	pp. 146 - 148
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R2-7 (Time: 16:22 - 16:24)

Title	Iddq Testing Against Process Variations and Measurement Noises
Author	Chia-Ling Chang, *Jack Sheng-Yan Lin, Clarles Hung-Pin Wen (National Chiao Tung Univ., Taiwan)
Page	pp. 149 - 150
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R2-8 (Time: 16:24 - 16:26)

Title	Pre-Bond Interposer Test Methodology for System in Package
Author	Katherine Shu-Min Li (National Sun Yat-sen Univ., Taiwan), Sying-Jyan Wang (National Chung Hsing Univ., Taiwan), Cheng-You Ho (National Sun Yat-sen Univ., Taiwan), Yingchieh Ho (National Dong Hwa Univ., Taiwan), Ruei-Ting Gu (National Sun Yat-sen Univ./Advanced Semiconductor Engineering (ASE) Group, Taiwan), Bo-Chuan Cheng (Advanced Semiconductor Engineering (ASE) Group, Taiwan)
Page	pp. 151 - 156
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R2-9 (Time: 16:26 - 16:28)

Title	Oxygen Sensor Module with Majority Sensing for Monitoring Wide Area at Disaster
Author	*Ryuta Nishino, Tatsuya Yamada, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)
Page	pp. 157 - 158
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R2-10 (Time: 16:28 - 16:30)

Title	FPGA Implementation and Evaluation of Image Scaling Circuits Using Seletor-Logic-Based Bi-Linear Interpolation
Author	*Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ., Japan)
Page	pp. 159 - 160
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R2-11 (Time: 16:30 - 16:32)

Title	An Accelerator for Frequent Itemset Mining from Data Stream with Parallel Item Tree
Author	*Kasho Yamamoto, Tsunaki Sadahisa, Dahoo Kim, Eric S. Fukuda, Tetsuya Asai, Masato Motomura (Hokkaido Univ., Japan)
Page	pp. 161 - 162
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R2-12 (Time: 16:32 - 16:34)

Title	A Leakage Current Reduction Algorithm Using Input Vector Control and Cell Topology Modification
Author	Tsung-Yi Wu (National Changhua Univ. of Education, Taiwan), Hsin-Hui Li (Global Unichip, Taiwan), *Zhi-Yao Ding, Guan-Cheng Guo (National Changhua Univ. of Education, Taiwan)
Page	pp. 163 - 164
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R2-13 (Time: 16:34 - 16:36)

Title	Majority-Inverter Graph for FPGA Synthesis
Author	*Luca Amaru (EPFL - LSI, Switzerland), Ana Petkovska (EPFL - LAP, Switzerland), Pierre-Emmanuel Gaillardon (EPFL - LSI, Switzerland), David Novo Bruna, Paolo Ienne (EPFL - LAP, Switzerland), Giovanni De Micheli (EPFL - LSI, Switzerland)
Page	pp. 165 - 170
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R2-14 (Time: 16:36 - 16:38)

Title	High Observability Scan Chains with Improving Output Compaction Efficiency
Author	Sying-Jyan Wang, Che-Wei Kao (National Chung Hsing Univ., Taiwan), Katherine Shu-Min Li (National Sun Yat-sen Univ., Taiwan)
Page	pp. 171 - 176
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R2-15 (Time: 16:38 - 16:40)

Title	Using Structural Relations for Checking Combinationality of Cyclic Circuits
Author	Wan-Chen Weng (National Tsing Hua Univ., Taiwan), Yung-Chih Chen (Yuan Ze Univ., Taiwan), Jui-Hung Chen, *Ching-Yi Huang, Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 177 - 182
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R2-16 (Time: 16:40 - 16:42)

Title	YAPSIM: Yet Another Parallel Logic Simulation Using GP-GPU
Author	*Takuya Hashiguchi, Yuichiro Mori, Masahiko Toyonaga, Michiaki Muraoka (Kochi Univ., Japan)
Page	pp. 183 - 186
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R2-17 (Time: 16:42 - 16:44)

Title	Technology Mapping Method for Low Power Consumption and High Performance in General-Synchronous Framework
Author	*Junki Kawaguchi, Yukihide Kohira (Univ. of Aizu, Japan)
Page	pp. 187 - 192
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R2-18 (Time: 16:44 - 16:46)

Title	A Quaternary Master-Slave Flip-Flop with Multiple Functions for Multi-Valued Logics
Author	*Renyuan Zhang, Mineo Kaneko (JAIST, Japan)
Page	pp. 193 - 198
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R2-19 (Time: 16:46 - 16:48)

Title	Quantitative Evaluations and Efficient Exploration for Optimal Partially-Programmable Circuits Generation
Author	*Takumi Tsuzuki (NAIST, Japan), Yuko Hara-Azumi (Tokyo Inst. of Tech., Japan), Shigeru Yamashita (Ritsumeikan Univ., Japan), Yasuhiko Nakashima (NAIST, Japan)
Page	pp. 199 - 204
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R2-20 (Time: 16:48 - 16:50)

Title	A Variability-Aware Energy-Efficient On-Chip Memory for Near-Threshold Operation Using Cell-Based Structure
Author	*Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 205 - 210
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R2-21 (Time: 16:50 - 16:52)

Title	An Efficient Calculation Method for Reliability Analysis of Logic Circuits
Author	*Masatoshi Tsushima, Yuichi Ikeda, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Page	pp. 211 - 216
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Tuesday, March 17, 2015

Keynote Speech II
Time: 8:30 - 9:30 Tuesday, March 17, 2015
Chair: Ting-Chi Wang (National Tsing Hua Univ., Taiwan)

K2-1 (Time: 8:30 - 9:30)

Title	Reliability and Robustness - Design and EDA to the Rescue!
Author	*Ulf Schlichtmann (Tech. Univ. München, Germany)
Page	p. 217
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Poster III
Time: 9:45 - 11:30 Tuesday, March 17, 2015
Chairs: Kazuhito Ito (Saitama Univ., Japan), Shigeru Yamashita (Ritsumeikan Univ., Japan)

R3-1 (Time: 9:45 - 9:47)

Title	New nMOS Dynamic Shift Registers for Driver Circuit of Small LCDs and Their Evaluations
Author	*Shinji Higa, Shuji Tsukiyama (Chuo Univ., Japan), Isao Shirakawa (Univ. of Hyogo, Japan)
Page	pp. 218 - 223
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R3-2 (Time: 9:47 - 9:49)

Title	A Floorplan-Driven High-Level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs
Author	*Koichi Fujiwara, Masao Yanagisawa, Nozomu Togawa (Waseda Univ., Japan)
Page	pp. 224 - 225
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R3-3 (Time: 9:49 - 9:51)

Title	Introducing Loop Statements in Random Testing of C Compilers Based on Expected Value Calculation
Author	*Kazuhiro Nakamura, Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
Page	pp. 226 - 227
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R3-4 (Time: 9:51 - 9:53)

Title	Product Term Minimization in ROBDDs with Application to Reconfigurable SET Array Synthesis
Author	*Yi-Hang Chen, Yang Chen, Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Page	pp. 228 - 231
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R3-5 (Time: 9:53 - 9:55)

Title	An Effective Timing-Coherent Transactor Generation Approach for Mixed-Level System Simulations
Author	*Hsin-I Wu, Li-chun Chen, Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Page	pp. 232 - 237
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R3-6 (Time: 9:55 - 9:57)

Title	An Accurate Processor Power Estimation Approach Based on Microcomponent Structure Analysis
Author	*Chi-Kang Chen, Zih-Ci Huang, Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Page	pp. 238 - 243
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R3-7 (Time: 9:57 - 9:59)

Title	A Verilog Compiler Proposal for VerCPU Simulator
Author	*Tze Sin Tan (Altera, Malaysia), Bakhtiar Affendi Rosdi (Univ. Sains Malaysia, Malaysia)
Page	pp. 244 - 249
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R3-8 (Time: 9:59 - 10:01)

Title	MorFPGA Duo: A Dual-Core FPGA-Based Embedded System Development Platform
Author	Chih-Chyau Yang, *Chun-Yu Chen, Chun-Wen Cheng, Yi-Jun Liu, Chien-Ming Wu, Chun-Ming Huang (National Chip Implementation Center, Taiwan)
Page	pp. 250 - 254
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R3-9 (Time: 10:01 - 10:03)

Title	A 3G-Based Bridge Structural Health Monitoring System Using Cost-Effective 1-Axis Accelerometers
Author	Chih-Hsing Lin, *Wen-Ching Chen, Chih-Ting Kuo, Gang-Neng Sung, Chih-Chyau Yang, Chien-Ming Wu, Chun-Ming Huang (National Chip Implementation Center, Taiwan)
Page	pp. 255 - 259
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R3-10 (Time: 10:03 - 10:05)

Title	Analytical Reliability Model of Die-Stacked DRAM Protected by Error Control Code and TSV Fault Tolerant Coding Technique
Author	*Tadayuki Matsumura, Tsuyoshi Tanaka (Hitachi, Japan)
Page	pp. 260 - 265
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R3-11 (Time: 10:05 - 10:07)

Title	Protection Method for AES IP Core from Scan-Based Attack
Author	*Yifan Wu, Shinji Kimura (Waseda Univ., Japan)
Page	pp. 266 - 271
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R3-12 (Time: 10:07 - 10:09)

Title	Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing in Triple Algorithm Redundancy
Author	*Junghoon Oh, Mineo Kaneko (JAIST, Japan)
Page	pp. 272 - 277
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R3-13 (Time: 10:09 - 10:11)

Title	Using Range-Equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking
Author	Yung-Chih Chen (Yuan Ze Univ., Taiwan), Wei-An Ji, Chih-Chung Wang, *Ching-Yi Huang, Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 278 - 282
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R3-14 (Time: 10:11 - 10:13)

Title	Design of PPG-Based Heart Rate Sensor Enabling Motion Artifact Cancellation
Author	*Takunori Shimazaki, Shinsuke Hara (Osaka City Univ., Japan)
Page	pp. 283 - 286
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R3-15 (Time: 10:13 - 10:15)

Title	A Redundant Task Allocation Method for Reliable Network-on-Chips
Author	*Hiroshi Saito (Univ. of Aizu, Japan), Tomohiro Yoneda (NII, Japan), Yuichi Nakamura (NEC, Japan)
Page	pp. 287 - 292
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R3-16 (Time: 10:15 - 10:17)

Title	Single-Flux-Quantum Digital Circuit Design Using Clockless Logic Cells with a Jitter Constraint
Author	*Ryohei Matsumoto, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Page	pp. 293 - 298
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R3-17 (Time: 10:17 - 10:19)

Title	Time Analysis of Applying Back Gate Bias for Reconfigurable Architectures with SOTB MOSFET
Author	*Hayate Okuhara, Hideharu Amano (Keio Univ., Japan)
Page	pp. 299 - 304
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R3-18 (Time: 10:19 - 10:21)

Title	A Cooling Effect Formulation and Implementation of a Cooling System for Li-Ion Battery Modules
Author	*Yuki Kitagawa, Yusuke Yamamoto, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 305 - 310
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R3-19 (Time: 10:21 - 10:23)

Title	Global Transformation-Based Optimization of Threshold Logic Circuits
Author	*Maiko Kabu, Takayuki Kasugai, Shigeru Yamashita (Ritsumeikan Univ., Japan), Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 311 - 316
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R3-20 (Time: 10:23 - 10:25)

Title	Counter-Based Victim Cache Hit Rate Optimization
Author	*Li-Yen Chang, Chen-Hua Suo, Yi-Yu Liu (Yuan Ze Univ., Taiwan)
Page	pp. 317 - 318
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R3-21 (Time: 10:25 - 10:27)

Title	An ECO-Friendly Design Style Based on Reconfigurable Cells
Author	*Yudai Kabata, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 319 - 324
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Invited Talk II
Time: 13:00 - 13:50 Tuesday, March 17, 2015
Chair: Mineo Kaneko (JAIST, Japan)

I2-1 (Time: 13:00 - 13:50)

Title	A New Approach to Synthesis of Transition Signaling Asynchronous Circuits
Author	*Tomohiro Yoneda (NII, Japan)
Page	p. 325
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Invited Talk III
Time: 14:05 - 14:55 Tuesday, March 17, 2015
Chair: Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)

I3-1 (Time: 14:05 - 14:55)

Title	IC Design Challenges and Opportunities in Advanced Process Nodes
Author	*Hsien-Hsin Sean Lee (TSMC, Taiwan)
Page	p. 326
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Poster IV
Time: 14:55 - 16:40 Tuesday, March 17, 2015
Chairs: Atsushi Takahashi (Tokyo Inst. of Tech., Japan), Ing-Jer Huang (National Sun Yat-sen Univ., Taiwan)

R4-1 (Time: 14:55 - 14:57)

Title	Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults - from Device to Circuit Level
Author	Hsuan-Ming Huang, *Yi-Wu Liu, Charles H.-P. Wen (National Chiao Tung Univ., Taiwan)
Page	pp. 327 - 332
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R4-2 (Time: 14:57 - 14:59)

Title	Using Body Biasing for Energy Efficient Frequency Scaling in a Dynamically Reconfigurable Processor
Author	*Johannes Maximilian Kühn (Univ. of Tübingen, Germany), Hideharu Amano (Keio Univ., Japan), Wolfgang Rosenstiel (Univ. of Tübingen, Germany)
Page	pp. 333 - 338
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R4-3 (Time: 14:59 - 15:01)

Title	Low-Power Gated Clock Tree Synthesis for 3D ICs
Author	*Yu-Chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin (National Chung Cheng Univ., Taiwan)
Page	pp. 339 - 343
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R4-4 (Time: 15:01 - 15:03)

Title	Graph-Covering-Based Architectural Synthesis for Programmable Digital Microfluidic Biochips
Author	*Daiki Kitagawa, Dieu Quang Nguyen, Trung Anh Dinh, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Page	pp. 344 - 349
Detailed information (abstract, keywords, etc)

R4-5 (Time: 15:03 - 15:05)

Title	Contamination-Aware Routing Flow for Both Functional and Washing Droplets in Digital Microfluidic Biochips
Author	*Qin Wang, Yiren Shen, Hailong Yao (Tsinghua Univ., China), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan), Yici Cai (Tsinghua Univ., China)
Page	pp. 350 - 355
Detailed information (abstract, keywords, etc)
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R4-6 (Time: 15:05 - 15:07)

Title	Obstacle-Avoiding Wind Turbine Placement for Power-Loss and Wake-Effect Optimization
Author	*Yu-Wei Wu (National Cheng Kung Univ., Taiwan), Yi-Yu Shi (Missouri Univ. of Science and Tech., U.S.A.), Sudip Roy (National Cheng Kung Univ., Taiwan), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan)
Page	pp. 356 - 361
Detailed information (abstract, keywords, etc)

R4-7 (Time: 15:07 - 15:09)

Title	Accelerating Random-Walk-Based Power Grid Analysis through Error Smoothing
Author	*Tsuyoshi Okazaki, Masayuki Hiromoto, Takashi Sato (Kyoto Univ., Japan)
Page	pp. 362 - 367
Detailed information (abstract, keywords, etc)

R4-8 (Time: 15:09 - 15:11)

Title	Improvement of Simulated Annealing Search ---Based on Tree Representations---
Author	*Takaaki Banno, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan)
Page	pp. 368 - 373
Detailed information (abstract, keywords, etc)
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R4-9 (Time: 15:11 - 15:13)

Title	A Hierarchical Type Segmentation Algorithm Based on Support Vector Machine for Colorectal Endoscopic Images with NBI Magnification
Author	*Takumi Okamoto, Tetsushi Koide, Anh-Tuan Hoang, Koki Sugi, Tatsuya Shimizu, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka (Hiroshima Univ., Japan)
Page	pp. 374 - 379
Detailed information (abstract, keywords, etc)
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R4-10 (Time: 15:13 - 15:15)

Title	High Performance Feature Transformation Architecture Based on Bag-of-Features in CAD System for Colorectal Endoscopic Images
Author	*Koki Sugi, Tetsushi Koide, Anh-Tuan Hoang, Takumi Okamoto, Tatsuya Shimizu, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka (Hiroshima Univ., Japan)
Page	pp. 380 - 385
Detailed information (abstract, keywords, etc)
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R4-11 (Time: 15:15 - 15:17)

Title	Hardware Implementation of Motion Estimation Technology Using High Level Synthesis and Investigations into Techniques for Improvements
Author	*Shota Nagai, Takashi Kambe (Kindai Univ., Japan), Gen Fujita (Osaka Electro-Communication Univ., Japan)
Page	pp. 386 - 390
Detailed information (abstract, keywords, etc)
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R4-12 (Time: 15:17 - 15:19)

Title	FPGA Oriented Intra Angular Prediction Image Generation Hardware for HEVC Video Coding
Author	*Eita Kobayashi, Seiya Shibata, Noriaki Suzuki, Atsufumi Shibayama, Takeo Hosomi (NEC, Japan)
Page	pp. 391 - 396
Detailed information (abstract, keywords, etc)
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R4-13 (Time: 15:19 - 15:21)

Title	High Accuracy and Simple Real-Time Circle Detection on Low-Cost FPGA for Traffic-Sign Recognition on Advanced Driver Assistance System
Author	*Anh-Tuan Hoang, Masaharu Yamamoto, Tetsushi Koide (Hiroshima Univ., Japan)
Page	pp. 397 - 402
Detailed information (abstract, keywords, etc)
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R4-14 (Time: 15:21 - 15:23)

Title	DMATP: A Design Method and Architecture of TU Parallel Processing for 4K HEVC Hardware Encoder
Author	*Seiya Shibata, Eita Kobayashi, Noriaki Suzuki, Atsufumi Shibayama, Takeo Hosomi (NEC, Japan)
Page	pp. 403 - 408
Detailed information (abstract, keywords, etc)
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R4-15 (Time: 15:23 - 15:25)

Title	An Improved Rate-Distortion Optimized Quantization Algorithm and Its Hardware Implementation
Author	*Genki Moriguchi, Takashi Kambe (Kindai Univ., Japan), Gen Fujita (Osaka Electro-Communication Univ., Japan)
Page	pp. 409 - 414
Detailed information (abstract, keywords, etc)
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R4-16 (Time: 15:25 - 15:27)

Title	Implementation and Evaluation of AES/ADPCM on STP and FPGA with High-Level Synthesis
Author	*Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ., Japan)
Page	pp. 415 - 420
Detailed information (abstract, keywords, etc)
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R4-17 (Time: 15:27 - 15:29)

Title	Speed Traffic-Sign Number Recognition on Low Cost FPGA for Robust Sign Distortion and Illumination Conditions
Author	*Masaharu Yamamoto, Anh-Tuan Hoang, Tetsushi Koide (Hiroshima Univ., Japan)
Page	pp. 421 - 426
Detailed information (abstract, keywords, etc)
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R4-18 (Time: 15:29 - 15:31)

Title	Efficient Manipulation of Truth Tables on CUDA for Gate-Level Simulation
Author	*Yuri Ardila, Tatsuyuki Kida, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Page	pp. 427 - 432
Detailed information (abstract, keywords, etc)

R4-19 (Time: 15:31 - 15:33)

Title	Scan-Based Side-Channel Attack Implementation Evaluation on the LED Cipher Using SASEBO-GII
Author	*Huiqian Jiang, Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa (Waseda Univ., Japan)
Page	pp. 433 - 434
Detailed information (abstract, keywords, etc)

R4-20 (Time: 15:33 - 15:35)

Title	A Study on Visualization of Auscultation-Based Blood Pressure Measurement
Author	*Yusuke Katsuki, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)
Page	pp. 435 - 436
Detailed information (abstract, keywords, etc)
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SASIMI 2015 The 19th Workshop on Synthesis And System Integration of Mixed Information Technologies Technical Program

Session Schedule

List of papers

SASIMI 2015
The 19th Workshop on Synthesis And System Integration of Mixed Information Technologies
Technical Program