SASIMI 2016
The 20th Workshop on Synthesis And System Integration of Mixed Information Technologies
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Monday, October 24, 2016


Registration - 9:00
Opening 9:00 - 9:20
K Keynote Speech 9:20 - 10:20
R1 POSTER I 10:20 - 11:50
Lunch 11:50 - 13:20
I1 Invited Talk 13:20 - 14:10
R2 POSTER II 14:10 - 15:40
20th Memorial Ceremony 15:40 - 15:55
D Panel 15:55 - 17:40

Tuesday, October 25, 2016


I2 Invited Talk 9:10 - 10:00
R3 POSTER III 10:00 - 11:50
Lunch 11:50 - 13:20
I3 Invited Talk 13:20 - 14:10
R4 POSTER IV 14:10 - 16:00
I4 Invited Talk 16:00 - 16:50
Closing 16:50 - 17:00

List of papers

Remark: The presenter of each paper is marked with "*".

Monday, October 24, 2016

Keynote Speech
Time: 9:20 - 10:20 Monday, October 24, 2016
Chair: Nagisa Ishiura (Kwansei Gakuin Univ., Japan)

K-1 (Time: 9:20 - 10:20)

Title	Cyber-Medical Systems: Requirements, Components and Design
Author	*Giovanni De Micheli (EPFL, Switzerland)
Page	p. 1
Detailed information (abstract, keywords, etc)
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POSTER I
Time: 10:20 - 11:50 Monday, October 24, 2016
Chairs: Yoshinori Takeuchi (Osaka Univ., Japan), Kazuya Tanigawa (Hiroshima City Univ., Japan)

R1-1 (Time: 10:20 - 10:22)

Title	Detecting Missed Arithmetic Optimization in C Compilers by Differential Random Testing
Author	*Mitsuyoshi Iwatsuji, Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
Page	pp. 2 - 3
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R1-2 (Time: 10:22 - 10:24)

Title	Symmetric Segmented Delta Encoding for Wireless Sensor Data Compression
Author	*Shu-Ping Liang, Yi-Yu Liu (Yuan Ze Univ., Taiwan)
Page	pp. 4 - 9
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R1-3 (Time: 10:24 - 10:26)

Title	Register-Bridge Architecture and its Application to Multiprocessor Systems
Author	*Takafumi Fujii, Shinichi Nishizawa, Kazuhito Ito (Saitama Univ., Japan)
Page	pp. 10 - 15
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R1-4 (Time: 10:26 - 10:28)

Title	Hardware Accelerator of Convolutional Neural Network for Image Recognition and its Performance Evaluation Platform
Author	*Takayuki Ujiie, Masayuki Hiromoto, Takashi Sato (Kyoto Univ., Japan)
Page	pp. 16 - 17
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R1-5 (Time: 10:28 - 10:30)

Title	On a Radiation Resistant Data-Path and Controller Synthesis
Author	*Keisuke Inoue (Kanazawa Technical College, Japan)
Page	pp. 18 - 22
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R1-6 (Time: 10:30 - 10:32)

Title	A Heuristic Decompositions Index Generation Functions with Many Variables
Author	Tsutomu Sasao, *Kyu Matsuura, Yukihiro Iguchi (Meiji Univ., Japan)
Page	pp. 23 - 28
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R1-7 (Time: 10:32 - 10:34)

Title	Debugging of Reconfigurable Single-Electron Transistor Arrays
Author	Wen-Chun Zeng, *Shih-Hsiang Liu, Yu-Da Chen, Yung-Chih Chen (Yuan Ze Univ., Taiwan)
Page	pp. 29 - 30
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R1-8 (Time: 10:34 - 10:36)

Title	Layer Assignment for Multi-Power-Mode 3D IC Designs with Power Distribution Networks Considered
Author	*Shih-Hsu Huang, Jian-Zhi Shen, Chun-Hua Cheng (Chung Yuan Christian Univ., Taiwan)
Page	pp. 31 - 35
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R1-9 (Time: 10:36 - 10:38)

Title	A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory
Author	*Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 36 - 41
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R1-10 (Time: 10:38 - 10:40)

Title	CORP: Control Routing for Paper-Based Digital Microfluidic Biochips
Author	Qin Wang, Hailong Yao (Tsinghua Univ., China), *Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Yici Cai (Tsinghua Univ., China)
Page	pp. 42 - 47
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R1-11 (Time: 10:40 - 10:42)

Title	Analysis of Body Bias Control for Real Time Systems
Author	*Carlos Cesar Cortes Torres, Hayate Okuhara, Akram Ben Ahmed, Nobuyuki Yamasaki, Hideharu Amano (Keio Univ., Japan)
Page	pp. 48 - 53
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R1-12 (Time: 10:42 - 10:44)

Title	Performance-Driven Multi-Layer OARST Construction with Steiner-Point Pre-Selection and Bounded Maze Routing
Author	*Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li (National Chiao Tung Univ., Taiwan), Rung-Bin Lin (Yuan Ze Univ., Taiwan), Wen-Hao Liu (Cadence Design Systems, U.S.A.)
Page	pp. 54 - 59
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R1-13 (Time: 10:44 - 10:46)

Title	Performance Improvement of General-Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection
Author	*Shimpei Sato, Hiroshi Nakatsuka, Atsushi Takahashi (Tokyo Inst. of Tech., Japan)
Page	pp. 60 - 65
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R1-14 (Time: 10:46 - 10:48)

Title	FPGA Prototyping of a Smart Card Platform for Evaluating Tamper Resistance of Cryptographic Circuits
Author	*Hiroyuki Kanbara (ASTEM RI, Japan), Naoya Ito, Hinata Takebayashi (Kwansei Gakuin Univ., Japan), Muneyuki Takenae (Ritsumeikan Univ., Japan), Takashi Tsukamoto (Information-technology Promotion Agency, Japan)
Page	pp. 66 - 70
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R1-15 (Time: 10:48 - 10:50)

Title	Convolutional Neural Network Layer Reordering for Acceleration
Author	*Vijay Daultani, Subhajit Chaudhury, Kazuhisa Ishizaka (NEC, Japan)
Page	pp. 71 - 76
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R1-16 (Time: 10:50 - 10:52)

Title	System Design of Vision-based Framework for Senior Driver Assistance
Author	*Eric Aliwarga, Koichi Mitsunari, Jaehoon Yu, Takao Onoye (Osaka Univ., Japan), Toshitaka Azuma, Mitsuhiko Koga (Vehicle Information and Communication System Center, Japan)
Page	pp. 77 - 80
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R1-17 (Time: 10:52 - 10:54)

Title	An FPGA Implementation of SVM for Type Identification with Colorectal Endoscopic Images
Author	*Takumi Okamoto, Tetsushi Koide, Anh-Tuan Hoang, Tatsuya Shimizu, Koki Sugi, Toru Tamaki, Tsubasa Hirakawa, Bisser Raytchev, Kazufumi Kaneda (Hiroshima Univ., Japan), Shigeto Yoshida, Hiroshi Mieno (Hiroshima General Hospital of West Japan Railway Company, Japan), Shinji Tanaka (Hiroshima Univ. Hospital, Japan)
Page	pp. 81 - 86
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Invited Talk
Time: 13:20 - 14:10 Monday, October 24, 2016
Chair: Mineo Kaneko (JAIST, Japan)

I1-1 (Time: 13:20 - 14:10)

Title	Computing in the IoT Era, Opportunities and Challenges
Author	*David Chen (ARM, China)
Page	p. 87
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POSTER II
Time: 14:10 - 15:40 Monday, October 24, 2016
Chairs: Masato Inagi (Hiroshima City Univ., Japan), Seiya Shibata (NEC, Japan)

R2-1 (Time: 14:10 - 14:12)

Title	Random Testing of Back-end of Compiler Infrastructure LLVM
Author	*Kenji Tanaka, Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Masanari Nishimura, Akiya Fukui (Renesas System Design, Japan)
Page	pp. 88 - 89
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R2-2 (Time: 14:12 - 14:14)

Title	Retention-aware Refresh Techniques for DRAM Refresh Power Reduction
Author	*Wei-Kai Cheng, Po-Yuan Shen (Chung Yuan Christian Univ., Taiwan)
Page	pp. 90 - 93
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R2-3 (Time: 14:14 - 14:16)

Title	Stochastic Number Generation with Internal Signals of Logic Circuits
Author	*Naoya Kubota, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ., Japan)
Page	pp. 94 - 95
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R2-4 (Time: 14:16 - 14:18)

Title	A Branch-and-Bound Algorithm for Scheduling of Data-Parallel Tasks
Author	*Yang Liu, Lin Meng, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ., Japan)
Page	pp. 96 - 100
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R2-5 (Time: 14:18 - 14:20)

Title	Automatic Enable Candidate Extraction for Backward Sequential Clock Gating
Author	*Shinji Kimura, Tomoya Goto, Masao Yanagisawa (Waseda Univ., Japan)
Page	pp. 101 - 106
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R2-6 (Time: 14:20 - 14:22)

Title	A Decision Diagram to Analyze Probabilistic Behavior of Circuits
Author	*Kodai Abe, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Page	pp. 107 - 112
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R2-7 (Time: 14:22 - 14:24)

Title	Random Delay Elements for Tamper Resistant Asynchronous Circuits based on 2-phase Handshaking Protocol
Author	*Daiki Toyoshima, Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ., Japan)
Page	pp. 113 - 118
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R2-8 (Time: 14:24 - 14:26)

Title	Optimization of Temperature Dependent Intentional Skew for Temperature Aware Timing Design
Author	*Makoto Soga, Mineo Kaneko (JAIST, Japan)
Page	pp. 119 - 124
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R2-9 (Time: 14:26 - 14:28)

Title	Performance Evaluation Platform for Programmable Interconnect Architecture Exploration
Author	Kohei Yamamoto, Toshiki Morioka, Tomoya Inoue, *Masataka Mori, Yukio Mitsuyama (Kochi Univ. of Tech., Japan)
Page	pp. 125 - 128
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R2-10 (Time: 14:28 - 14:30)

Title	Efficient Standard Cell Layout Synthesis Algorithm Considering Various Driving Strengths
Author	*Hong-Yan Su, Bo-Shung Wang, Sin-Ye Hsieh, Yih-Lang Li (National Chiao Tung Univ., Taiwan), I-Hsun Wu, Chang-Chung Wu, Wei-Chiang Shih (M31 Technology, Taiwan), Hidetoshi Onodera (Kyoto Univ., Japan), Masanori Hashimoto (Osaka Univ., Japan)
Page	pp. 129 - 134
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R2-11 (Time: 14:30 - 14:32)

Title	Fast Length-Matching Routing for Rapid Single Flux Quantum Circuits
Author	*Nobutaka Kito (Chukyo Univ., Japan), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ., Japan)
Page	pp. 135 - 140
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R2-12 (Time: 14:32 - 14:34)

Title	A Comparative Study on Multisource Clock Network Synthesis
Author	Wen-Hsin Chen, Chun-Kai Wang, *Hung-Ming Chen (NCTU Taiwan, Taiwan), Yih-Chih Chen, Cheng-Hong Tsai (Global Unichip, Taiwan)
Page	pp. 141 - 145
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R2-13 (Time: 14:34 - 14:36)

Title	Target Concentration Exploration for Reactant Minimization on Digital Microfluidic Biochips
Author	Yi-Ling Chen, Yung-Chun Lei, *Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Page	pp. 146 - 151
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R2-14 (Time: 14:36 - 14:38)

Title	Practical and Accurate SOC Estimation System for Lithium-Ion Batteries by EKF with Adaptive Noise Covariance Estimation
Author	*Lei Lin, Kiyotsugu Takaba, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 152 - 157
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R2-15 (Time: 14:38 - 14:40)

Title	True Random-Bit Generation Using a Continuous-Time Chaotic Oscillator
Author	*Chatchai Wannaboon, Masayoshi Tachibana (Kochi Univ. of Tech., Japan)
Page	pp. 158 - 161
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R2-16 (Time: 14:40 - 14:42)

Title	Hardware Acceleration Technique for Radio-resource Scheduler in Ultra-high-density Distributed Antenna Systems
Author	*Yuki Arikawa, Hiroyuki Uzawa, Takeshi Sakamoto, Satoshi Shigematsu (NTT, Japan)
Page	pp. 162 - 163
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R2-17 (Time: 14:42 - 14:44)

Title	An Overlay Architecture for FPGA-Based Industrial Control Systems Designed with Functional Block Diagrams
Author	*Taisei Segawa, Yuichiro Shibata, Yudai Shirakura, Kenichi Morimoto, Hidenori Maruta, Fujio Kurokawa (Nagasaki Univ., Japan), Masaharu Tanaka (Mitsubishi Heavy Industries, Japan), Masanori Nobe (Mitsubishi Hitachi Power Systems, Japan)
Page	pp. 164 - 169
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Panel
Time: 15:55 - 17:40 Monday, October 24, 2016

D-1 (Time: 15:55 - 17:25)

Title	Past and Future 25 Years of Synthesis and System Integration
Author	Moderator: Isao Shirakawa (Univ. of Hyogo, Japan), Panelists: Giovanni De Micheli (EPFL, Switzerland), Youn-Long Lin, Ren-Song Tsay (National Tsing Hua Univ., Taiwan), Peter Marwedel (Technical Univ. of Dortmund, Germany), Organizer: Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
Page	p. 170
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Tuesday, October 25, 2016

Invited Talk
Time: 9:10 - 10:00 Tuesday, October 25, 2016
Chair: Kiyoharu Hamaguchi (Shimane Univ., Japan)

I2-1 (Time: 9:10 - 10:00)

Title	Wide Bandgap Analog and Mixed-signal IC Design for Advanced Power Electronics
Author	*Alan Mantooth (Univ. of Arkansas, U.S.A.)
Page	p. 171
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POSTER III
Time: 10:00 - 11:50 Tuesday, October 25, 2016
Chairs: Wenxing Zhu (Fuzhou Univ., China), Hideki Takase (Kyoto Univ., Japan)

R3-1 (Time: 10:00 - 10:02)

Title	Extending Distributed Control for High-Level Synthesis beyond Borders of Basic Blocks
Author	*Miho Shimizu, Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
Page	pp. 172 - 177
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R3-2 (Time: 10:02 - 10:04)

Title	Proposal of an Efficient Clock-Gating Mechanism for Multi-Core Processors to Reduce Power Supply Noise
Author	*Jun Kawabe, Yoshinori Takeuchi, Jaehoon Yu, Masaharu Imai (Osaka Univ., Japan)
Page	pp. 178 - 183
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R3-3 (Time: 10:04 - 10:06)

Title	Automatic Netlist Transformation for WDF-Based Analog Emulator
Author	Hsu-Ping Yang, *Hsin-Ju Hsu, Chun Wang, Chien-Nan Jimmy Liu, Jing-Yang Jou (National Central Univ., Taiwan)
Page	pp. 184 - 189
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R3-4 (Time: 10:06 - 10:08)

Title	Nonlinear Optimization Solver with Multiple Precision Arithmetic
Author	*Yuya Matsumoto, Hiroshige Dan (Kansai Univ., Japan)
Page	pp. 190 - 194
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R3-5 (Time: 10:08 - 10:10)

Title	High Speed Cycle-Accurate Processor Simulation Through Ahead of Time Compilation
Author	*Lovic Gauthier (National Inst. of Tech., Ariake College, Japan)
Page	pp. 195 - 200
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R3-6 (Time: 10:10 - 10:12)

Title	Prototype Speed Limit Sign Recognition System Implementation on Rapid Prototyping Platform
Author	*Anh-Tuan Hoang, Takumi Okamoto, Tetsushi Koide (Hiroshima Univ., Japan)
Page	pp. 201 - 202
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R3-7 (Time: 10:12 - 10:14)

Title	Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks
Author	*Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura (Hokkaido Univ., Japan)
Page	pp. 203 - 204
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R3-8 (Time: 10:14 - 10:16)

Title	On Component Ratio of RECON Spare Cells for ECO-Friendly Design Style
Author	*Takeshi Sawai, Ayano Takezaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 205 - 210
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R3-9 (Time: 10:16 - 10:18)

Title	Theorem-proving Verification of Multi-clock Synchronous Circuits on Multimodal Logic
Author	*Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ., Japan)
Page	pp. 211 - 212
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R3-10 (Time: 10:18 - 10:20)

Title	Hardware Trojan Insertion Difficulties into Synchronous and Asynchronous Circuits
Author	*Masashi Imai (Hirosaki Univ., Japan), Tomohiro Yoneda (NII, Japan)
Page	pp. 213 - 218
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R3-11 (Time: 10:20 - 10:22)

Title	A Delay Adjustment Method for Asynchronous Circuits with Bundled-data Implementation Considering a Latency Constraint
Author	*Kazumasa Yoshimi, Hiroshi Saito (Univ. of Aizu, Japan)
Page	pp. 219 - 224
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R3-12 (Time: 10:22 - 10:24)

Title	Path Grouping Approach for Efficient Candidate Selection of Replacing NBTI Mitigation Logic
Author	*Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato (Kyoto Univ., Japan)
Page	pp. 225 - 230
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R3-13 (Time: 10:24 - 10:26)

Title	Semi-Automated Analog Placement based on Margin Tolerances
Author	*Eric Lao, Marie-Minerve Louërat, Jean-Paul Chaput (Laboratoire d'informatique de Paris 6, France)
Page	pp. 231 - 235
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R3-14 (Time: 10:26 - 10:28)

Title	An Efficient Gaussian Mixture Reduction to Two Components
Author	Naoya Yokoyama, *Daiki Azuma, Shuji Tsukiyama (Chuo Univ., Japan), Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 236 - 241
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R3-15 (Time: 10:28 - 10:30)

Title	Thermal Circuit Identification of Power MOSFETs through In-Situ Channel Temperature Estimation
Author	*Kazuki Oishi, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato (Kyoto Univ., Japan)
Page	pp. 242 - 247
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R3-16 (Time: 10:30 - 10:32)

Title	Evaluation of PLL Layouts based on Transistor Array-style
Author	*Atsushi Nanri, Bo Liu, Yuki Miura, Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)
Page	pp. 248 - 251
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R3-17 (Time: 10:32 - 10:34)

Title	Single Row Cell Placement Considering Self-aligned Double Patterning
Author	Ye-Hong Chen, *Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 252 - 257
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R3-18 (Time: 10:34 - 10:36)

Title	A Lithium Ion Battery Aging Simulator with Calibration Functions
Author	*Yukinori Hayakawa, Lei Lin, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 258 - 263
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R3-19 (Time: 10:36 - 10:38)

Title	A Full Charge Capacity Estimation Algorithm for Li-ion Batteries Based on Recursive Least-Squares Identification with Adaptive Forgetting Factor Tuning
Author	*Hironori Ono, Lei Lin, Masahiro Fukui, Kiyotsugu Takaba (Ritsumeikan Univ., Japan)
Page	pp. 264 - 267
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R3-20 (Time: 10:38 - 10:40)

Title	A Hardware Architecture to Perform K-means Clustering for Learning-Based Super-Resolution Combining Self-Learning and Prior-Learning Dictionaries
Author	*Daichi Murata, Ayumi Kiriyama, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 268 - 273
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R3-21 (Time: 10:40 - 10:42)

Title	On-Chip Temperature Sensing using a Reconfigurable Ring Oscillator
Author	*Tadashi Kishimoto, Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 274 - 279
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R3-22 (Time: 10:42 - 10:44)

Title	A Shift HSV Algorithm for a Low-Power Monitoring System using an FPGA toward Internet of Things Agriculture
Author	Takahisa Kurose (Ehime Univ., Japan), *Hiroki Nakahara, Shimpei Sato (Tokyo Inst. of Tech., Japan), Tetsuo Morimoto (Ehime Univ., Japan)
Page	pp. 280 - 281
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Invited Talk
Time: 13:20 - 14:10 Tuesday, October 25, 2016
Chair: Kiyoharu Hamaguchi (Shimane Univ., Japan)

I3-1 (Time: 13:20 - 14:10)

Title	The Challenges and Future of Electronic-System Level Design Automation
Author	*Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Page	p. 282
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POSTER IV
Time: 14:10 - 16:00 Tuesday, October 25, 2016
Chairs: Tsuyoshi Matsumoto (Ishikawa Tech. College, Japan), Xin Jin (Tsinghua Univ., China)

R4-1 (Time: 14:10 - 14:12)

Title	Mathematical Algorithm Hardware Description Languages for System Level Modeling
Author	Ryo Hikawa, *Ryuji Kishimoto, Takashi Kambe (Kindai Univ., Japan)
Page	pp. 283 - 284
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R4-2 (Time: 14:12 - 14:14)

Title	High-Level Synthesis of Embedded Systems Controller from Erlang
Author	Hinata Takebayashi, Nagisa Ishiura, *Kagumi Azuma (Kwansei Gakuin Univ., Japan), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM RI, Japan)
Page	pp. 285 - 290
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R4-3 (Time: 14:14 - 14:16)

Title	A Data Effect Aware Microcomponent-Based Estimation Approach for Accurate System-Level Memory Device Power Evaluation
Author	*Chi-Kang Chen, Hsin-I Wu, Chi-Ting Hsiao, Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Page	pp. 291 - 296
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R4-4 (Time: 14:16 - 14:18)

Title	Analysis of Co-Controlling Voltage/Frequency of Cores and DRAMs of Chip Multi-Processors with 3D-stacked DRAMs for Thermal Management
Author	*Yi-Jung Chen (National Chi Nan Univ., Taiwan), Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu (National Taiwan Univ., Taiwan)
Page	pp. 297 - 302
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R4-5 (Time: 14:18 - 14:20)

Title	Introducing Real Constraints in Partitioned ILP-Based Binding in High-Level Synthesis
Author	Nagisa Ishiura, *Yuuki Oosako (Kwansei Gakuin Univ., Japan)
Page	pp. 303 - 304
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R4-6 (Time: 14:20 - 14:22)

Title	A Framework for Automatic Generation of Application-Specific FPGA-based SoC
Author	*Tetsuo Miyauchi, Kiyofumi Tanaka (JAIST, Japan)
Page	pp. 305 - 310
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R4-7 (Time: 14:22 - 14:24)

Title	Fast Song Searching by Simultaneous Execution of HiFP2.0 and Staged LSH
Author	*Masahiro Fukuda, Yasushi Inoguchi (JAIST, Japan)
Page	pp. 311 - 316
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R4-8 (Time: 14:24 - 14:26)

Title	An Error Diagnosis Technique Based on Averaged EPI Values to Extract Error Locations Sets
Author	*Ayano Takezaki, Takeshi Sawai, Hiroyuki Sakamoto, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 317 - 322
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R4-9 (Time: 14:26 - 14:28)

Title	Minimum Energy Point Tracking under a Wide Range of PVT Conditions
Author	*Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 323 - 328
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R4-10 (Time: 14:28 - 14:30)

Title	Comparison of Area-Delay-Energy Characteristics between General Purpose Processors and Dedicated Hardwares for Embedded Applications
Author	*Kei Yoshizawa, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 329 - 334
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R4-11 (Time: 14:30 - 14:32)

Title	Finding Effective Simulation Patterns for Coverage-Driven Verification Using Deep Learning
Author	*Mami Miyamoto, Kiyoharu Hamaguchi (Shimane Univ., Japan)
Page	pp. 335 - 340
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R4-12 (Time: 14:32 - 14:34)

Title	Static Timing Analysis of Rapid Single-Flux-Quantum Circuits
Author	*Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ., Japan)
Page	pp. 341 - 345
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R4-13 (Time: 14:34 - 14:36)

Title	Improved Method of Simulated Annealing for Unreachable Solution Space
Author	*Hiroyuki Nakano, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan)
Page	pp. 346 - 351
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R4-14 (Time: 14:36 - 14:38)

Title	Application of Monte-Carlo Tree Search to Traveling-Salesman Problem
Author	Masato Shimomura, *Yasuhiro Takashima (Univ. of Kitakyushu, Japan)
Page	pp. 352 - 356
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R4-15 (Time: 14:38 - 14:40)

Title	Analog Characterization Module with D/A Converter Configuration
Author	*Daishi Isogai, Bo Liu, Futa Yoshinaka, Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)
Page	pp. 357 - 361
Detailed information (abstract, keywords, etc)

R4-16 (Time: 14:40 - 14:42)

Title	Range Limiter using Connection Bounding Box for SA-based Placement of Mixed-Grained Reconfigurable Architecture
Author	*Takashi Kishimoto (Ritsumeikan Univ., Japan), Wataru Takahashi, Kazutoshi Wakabayashi (NEC, Japan), Hiroyuki Ochi (Ritsumeikan Univ., Japan)
Page	pp. 362 - 367
Detailed information (abstract, keywords, etc)

R4-17 (Time: 14:42 - 14:44)

Title	A Smart Hybrid Memetic Algorithm for Thermal-Aware Non-Slicing Floorplanning
Author	*Jianli Chen, Yan Liu, Ziran Zhu, Wenxing Zhu (Fuzhou Univ., China)
Page	pp. 368 - 373
Detailed information (abstract, keywords, etc)

R4-18 (Time: 14:44 - 14:46)

Title	Hardware Acceleration of Rate-Distortion Optimized Quantization Algorithm
Author	*Yusuke Funayama, Takashi Kambe (Kindai Univ., Japan), Gen Fujita (Osaka Electro-Communication Univ., Japan)
Page	pp. 374 - 375
Detailed information (abstract, keywords, etc)
PDF file

R4-19 (Time: 14:46 - 14:48)

Title	Development of an Optimal Wireless Power Transfer System for Lithium-Ion Battery Charge
Author	*Yuto Honda, Lei Lin, Masahiro Fukui (Ritsumeikan Univ., Japan)
Page	pp. 376 - 381
Detailed information (abstract, keywords, etc)
PDF file

R4-20 (Time: 14:48 - 14:50)

Title	Design of a Fast Lock-in and Low-Power All-Digital Frequency Synthesizer with a Wide Tuning Range
Author	*Hao-Chiao Hong, Hung-Yi Wen (National Chiao Tung Univ., Taiwan), Hong-Yi Huang (National Taipei Univ., Taiwan)
Page	pp. 382 - 385
Detailed information (abstract, keywords, etc)

R4-21 (Time: 14:50 - 14:52)

Title	A Method for Recognizing a Breaking Sound of a Window Glass for Realizing a Low-power Security Surveillance System Using FPGA
Author	*Ryo Terafuji, Hiroyuki Ochi (Ritsumeikan Univ., Japan)
Page	pp. 386 - 390
Detailed information (abstract, keywords, etc)

R4-22 (Time: 14:52 - 14:54)

Title	Electromagnetic Analysis for a Lightweight Block Cipher Simon
Author	*Yusuke Nozaki, Yoshiya Ikezaki, Masaya Yoshikawa (Meijo Univ., Japan)
Page	pp. 391 - 396
Detailed information (abstract, keywords, etc)

Invited Talk
Time: 16:00 - 16:50 Tuesday, October 25, 2016
Chair: Mineo Kaneko (JAIST, Japan)

I4-1 (Time: 16:00 - 16:50)

Title	Qualitative-Modeling-Based Design for Silicon Neuronal Networks
Author	*Takashi Kohno (Univ. of Tokyo, Japan)
Page	p. 397
Detailed information (abstract, keywords, etc)
PDF file

SASIMI 2016 The 20th Workshop on Synthesis And System Integration of Mixed Information Technologies Technical Program

Session Schedule

List of papers

SASIMI 2016
The 20th Workshop on Synthesis And System Integration of Mixed Information Technologies
Technical Program