(Back to Session Schedule)

SASIMI 2012
The 17th Workshop on Synthesis And System Integration of Mixed Information Technologies

Poster I
Time: 10:15 - 12:00 Thursday, March 8, 2012
Location: Int'l Conf. Room & Mtg. Room 31
Chairs: Hiroaki Yoshida (Univ. of Tokyo, Japan), Tomoo Inoue (Hiroshima City Univ., Japan)

R1-1
TitleTOF-based 3-Dimensional Head-Tracking System for Repetitive Transcranial Magnetic Stimulation
Author*Ryo Ebisuwaki, Yoshihiro Yasumuro, Hiroshige Dan, Masahiko Fuyuki (Kansai Univ., Japan)
Pagepp. 2 - 5
Detailed information (abstract, keywords, etc)
PDF file

R1-2
TitleA High-speed H.264/AVC CABAC Decoder for 4K Video Utilizing Residual Data Accelerator
Author*Kenji Watanabe (Synthesis Corp., Japan), Gen Fujita (Osaka Electro-Communication Univ., Japan), Toru Homemoto, Ryoji Hashimoto (Osaka Univ., Japan)
Pagepp. 6 - 10
Detailed information (abstract, keywords, etc)
PDF file

R1-3
TitleLow Power Decision Tree-Based Flow Search Engine
Author*Eita Kobayashi, Norio Yamagaki, Takashi Takenaka, Satoshi Kamiya (NEC Corp., Japan), Masato Motomura (Hokkaido Univ., Japan)
Pagepp. 11 - 16
Detailed information (abstract, keywords, etc)
PDF file

R1-4
TitleManycore NOC Based 2400-PE Network on Chip Emulation and Verification Environment
Author*Omar Hammami (ENSTA ParisTech, France), Xinyu Li (EVE, France)
Pagepp. 17 - 21
Detailed information (abstract, keywords, etc)

R1-5
TitleBit-Selective SAD and Its Evaluation
AuthorRyosuke Hamaji, Yongson Choi, Yuko Hara-Azumi, *Shigeru Yamashita (Ritsumeikan Univ., Japan)
Pagepp. 22 - 27
Detailed information (abstract, keywords, etc)

R1-6
TitleA Technique for Accelerating SVM-Based Image Recognition Using GPU
Author*Jin Sasaki, Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 28 - 32
Detailed information (abstract, keywords, etc)

R1-7
TitleVariation of Substrate Sensitivity in Differential Pair Transistors
Author*Satoshi Takaya, Takashi Hasegawa, Yoji Bando (Kobe Univ., Japan), Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete, Japan), Makoto Nagata (Kobe Univ., Japan)
Pagepp. 33 - 35
Detailed information (abstract, keywords, etc)

R1-8
TitleAutomatic Generation of GNU Binutils and GDB for Custom Processors Based on Plug-in Method
AuthorTakahiro Kumura (NEC Corp., Japan), Soichiro Taga (Mitsubishi Electric Micro-Computer Application Software Co., Ltd., Japan), *Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Pagepp. 36 - 41
Detailed information (abstract, keywords, etc)
PDF file

R1-9
TitleAccelerating Regression Test of Compilers by Test Program Merging
Author*Takayuki Fukumoto (Kwansei Gakuin Univ., Japan), Kazushi Morimoto (Nomura Research Institute, Ltd., Japan), Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
Pagepp. 42 - 47
Detailed information (abstract, keywords, etc)
PDF file

R1-10
TitleRandom Testing of C Compilers Targeting Arithmetic Optimization
Author*Eriko Nagai (Kwansei Gakuin Univ., Japan), Hironobu Awazu (Fujitsu, Japan), Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Naoya Takeda (ITEC Hankyu Hanshin, Japan)
Pagepp. 48 - 53
Detailed information (abstract, keywords, etc)
PDF file

R1-11
TitleCompiler-Assisted Soft Error Correction by Duplicating Instructions for VLIW Architecture
AuthorYunrong Li, Jongwon Lee (Seoul National Univ., Republic of Korea), *Yohan Ko, Kyoungwoo Lee (Yonsei Univ., Republic of Korea), Yunheung Paek (Seoul National Univ., Republic of Korea)
Pagepp. 54 - 59
Detailed information (abstract, keywords, etc)
PDF file

R1-12
TitleCompiler Generation Method from ADL for ASIP Integrated Development Environment
Author*Yusuke Hyodo, Kensuke Murata (Osaka Univ., Japan), Takuji Hieda (Ritsumeikan Univ., Japan), Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Pagepp. 60 - 65
Detailed information (abstract, keywords, etc)
PDF file

R1-13
TitleMono-instruction Computer on a Dynamically Reconfigurable Gate Array
Author*Yuki Nihira, Minoru Watanabe (Shizuoka Univ., Japan)
Pagepp. 66 - 70
Detailed information (abstract, keywords, etc)
PDF file

R1-14
TitleASPE: an Abstruction Framework using ALU Arrays for Scalable Multiple FPGAs System
AuthorKenta Inakagata, *Takayuki Akamine, Hirokazu Morishita (Keio Univ., Japan), Yasunori Osana (Ryukyu Univ., Japan), Naoyuki Fujita (Japan Aerospace Exploration Agency, Japan), Hideharu Amano (Keio Univ., Japan)
Pagepp. 71 - 76
Detailed information (abstract, keywords, etc)
PDF file

R1-15
TitleRobust Register Files by Exploiting Asymmetric Soft Error Rate
Author*Yohan Ko, Kyoungwoo Lee (Yonsei Univ., Republic of Korea)
Pagepp. 77 - 81
Detailed information (abstract, keywords, etc)
PDF file

R1-16
TitlePerformance Comparison of RG-DTM PUF and Arbiter-based PUFs
Author*Kousuke Ogawa, Mitsuru Shiozaki, Kota Furuhashi, Kohei Hozumi, Takeshi Fujino (Ritsumeikan Univ., Japan)
Pagepp. 82 - 87
Detailed information (abstract, keywords, etc)

R1-17
TitleHardware Architecture for Accelerating Monte Carlo based SSTA using Generalized STA Processing Element
Author*Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ., Japan)
Pagepp. 88 - 93
Detailed information (abstract, keywords, etc)

R1-18
TitleHead-Tail Expressions for Interval Functions
Author*Infall Syafalni, Tsutomu Sasao (Kyushu Inst. of Tech., Japan)
Pagepp. 94 - 99
Detailed information (abstract, keywords, etc)

R1-19
TitleA Performance Monitoring Tool Suite for Software and SoC On-Chip Bus
Author*Yi-Hao Chang, Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)
Pagepp. 100 - 105
Detailed information (abstract, keywords, etc)

R1-20
TitleBackward Multiple Time-frame Expansion for Accelerating Sequential SAT
Author*Kousuke Torii, Kazuhiro Nakamura (Nagoya Univ., Japan), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ., Japan)
Pagepp. 106 - 110
Detailed information (abstract, keywords, etc)
PDF file

R1-21
TitleOn Optimization of Power Network Synthesis for Multiple Power Domain Designs
AuthorChieh-Jui Lee, Shih-Ying Liu, Chuan-Chia Huang, *Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Pagepp. 111 - 114
Detailed information (abstract, keywords, etc)
PDF file

R1-22
TitleThermal-Aware Placement for Hotspot Mitigation in 3D FPGAs
Author*Juinn-Dar Huang, Ya-Shih Huang, Mi-Yu Hsu, Han-Yuan Chang (National Chiao Tung Univ., Taiwan)
Pagepp. 115 - 120
Detailed information (abstract, keywords, etc)

R1-23
TitleEfficient Delay Cells for Wave Pipelined Multifunctional Unit
AuthorAtsushi Kurokawa, *Tatsuya Takaki, Masa-aki Fukase (Hirosaki Univ., Japan)
Pagepp. 121 - 126
Detailed information (abstract, keywords, etc)

R1-24
TitleAn Integrated Smart Current Sensing Current-Mode Buck Converter
Author*Chia-Min Chen, Kai-Hsiu Hsu, Chung-Chih Hung (National Chiao Tung Univ., Taiwan)
Pagepp. 127 - 130
Detailed information (abstract, keywords, etc)
PDF file

R1-25
TitleLinear Time Estimation of Full-Chip Statistical Leakage Current
Author*Katsumi Homma (Fujitsu Laboratories Ltd., Japan)
Pagepp. 131 - 134
Detailed information (abstract, keywords, etc)
PDF file

R1-26
TitleAn Effective Overlap Removable Objective for Analytical Placement
Author*Syota Kuwabara, Yukihide Kohira (Univ. of Aizu, Japan), Yasuhiro Takashima (Univ. of Kitakyushu, Japan)
Pagepp. 135 - 140
Detailed information (abstract, keywords, etc)